SDRAM (Rev.1.1)
Single Data Rate
Feb.2000
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
CLK Suspension [CL=2, BL=4]
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
/CS
/RAS
/CAS
tRCD
/WE
CKE
DQM
A0-9,11 X
Y
Y
A10
X
A12
X
BA0,1
0
0
0
DQ
D0 D0
D0 D0
Q0 Q0 Q0 Q0
ACT#0 WRITE#0 internal CLK
suspended
READ#0
internal CLK
suspended
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
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