MAX669EUB/V-T Просмотр технического описания (PDF) - Maxim Integrated

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MAX669EUB/V-T

1.8V to 28V Input, PWM Step-Up Controllers in µMAX

Maxim Integrated 

1.8V to 28V Input, PWM Step-Up

Controllers in µMAX

not be adequate for low output voltage ripple. Since

output ripple in boost DC-DC designs is dominated by

capacitor equivalent series resistance (ESR), a capaci-

tance value 2 or 3 times larger than COUT(MIN) is typi-

cally needed. Low-ESR types must be used. Output

ripple due to ESR is:

VRIPPLE(ESR) = ILPEAK x ESRCOUT

Input Capacitor

The input capacitor (CIN) in boost designs reduces the

current peaks drawn from the input supply and reduces

noise injection. The value of CIN is largely determined

by the source impedance of the input supply. High

source impedance requires high input capacitance,

particularly as the input voltage falls. Since step-up DC-

DC converters act as “constant-power” loads to their

input supply, input current rises as input voltage falls.

Consequently, in low-input-voltage designs, increasing

CIN and/or lowering its ESR can add as many as five

percentage points to conversion efficiency. A good

starting point is to use the same capacitance value for

CIN as for COUT.

Bypass Capacitors

In addition to CIN and COUT, three ceramic bypass

capacitors are also required with the MAX668/MAX669.

Bypass REF to GND with 0.22µF or more. Bypass LDO

to GND with 1µF or more. And bypass VCC to GND with

0.1µF or more. All bypass capacitors should be located

as close to their respective pins as possible.

Compensation Capacitor

Output ripple voltage due to COUT ESR affects loop

stability by introducing a left half-plane zero. A small

capacitor connected from FB to GND forms a pole with

the feedback resistance that cancels the ESR zero. The

optimum compensation value is:

CFB

= COUT

x

ESRCOUT

(R2 x R3) / (R2 +

R3)

where R2 and R3 are the feedback resistors (Figures 2,

3, 4, and 5). If the calculated value for CFB results in a

non-standard capacitance value, values from 0.5CFB to

1.5CFB will also provide sufficient compensation.

Applications Information

Starting Under Load

In non-bootstrapped configurations (Figures 4 and 5),

the MAX668 can start up with any combination of out-

put load and input voltage at which it can operate when

already started. In other words, there are no special

limitations to start-up in non-bootstrapped circuits.

In bootstrapped configurations with the MAX668 or

MAX669, there may be circumstances where full load

current can only be applied after the circuit has started

and the output is near its set value. As the input voltage

drops, this limitation becomes more severe. This char-

acteristic of all bootstrapped designs occurs when the

MOSFET gate is not fully driven until the output voltage

rises. This is problematic because a heavily loaded out-

put cannot rise until the MOSFET has low on-resis-

tance. In such situations, low-threshold FETs (VTH <

VIN(MIN)) are the most effective solution. The Typical

Operating Characteristics section shows plots of start-

up voltage versus load current for a typical boot-

strapped design.

Layout Considerations

Due to high current levels and fast switching waveforms

that radiate noise, proper PC board layout is essential.

Protect sensitive analog grounds by using a star ground

configuration. Minimize ground noise by connecting

GND, PGND, the input bypass-capacitor ground lead,

and the output-filter ground lead to a single point (star

ground configuration). Also, minimize trace lengths to

reduce stray capacitance, trace resistance, and radiat-

ed noise. The trace between the external gain-setting

resistors and the FB pin must be extremely short, as

must the trace between GND and PGND.

Application Circuits

Low-Voltage Boost Circuit

Figure 3 shows the MAX669 operating in a low-voltage

boost application. The MAX669 is configured in the

bootstrapped mode to improve low input voltage per-

formance. The IRF7401 N-channel MOSFET was select-

ed for Q1 in this application because of its very low

0.7V gate threshold voltage (VGS). This circuit provides

a 5V output at greater than 2A of output current and

operates with input voltages as low as 1.8V. Efficiency

is typically in the 85% to 90% range.

+12V Boost Application

Figure 5 shows the MAX668 operating in a 5V to 12V

boost application. This circuit provides output currents

of greater than 1A at a typical efficiency of 92%. The

MAX668 is operated in non-bootstrapped mode to mini-

mize the input supply current. This achieves maximum

light-load efficiency. If input voltages below 5V are

used, the IC should be operated in bootstrapped mode

to achieve best low-voltage performance.

4-Cell to +5V SEPIC Power Supply

Figure 6 shows the MAX668 in a SEPIC (single-ended

primary inductance converter) configuration. This con-

figuration is useful when the input voltage can be either

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