LTC6945IUFDTRPBF Просмотр технического описания (PDF) - Linear Technology

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LTC6945IUFDTRPBF

Ultralow Noise and Spurious 0.35GHz to 6GHz Integer-N Synthesizer

Linear Technology 

LTC6945

OPERATION

PHASE/FREQUENCY DETECTOR (PFD)

The phase/frequency detector (PFD), in conjunction with

the charge pump, produces source and sink current pulses

proportional to the phase difference between the outputs

of the R and N dividers. This action provides the necessary

feedback to phase-lock the loop, forcing a phase align-

ment at the PFD’s inputs. The PFD may be disabled with

the CPRST bit which prevents UP and DOWN pulses from

being produced. See Figure 3 for a simplified schematic

of the PFD.

R DIV

N DIV

D

Q

RST

D

Q

RST

UP

CPRST

DELAY

DOWN

6945 F03

Figure 3. Simplified PFD Schematic

LOCK INDICATOR

The lock indicator uses internal signals from the PFD to

measure phase coincidence between the R and N divider

output signals. It is enabled by setting the LKEN bit in

the serial port register h07, and produces both LOCK and

UNLOCK status flags, available through both the STAT

output and serial port register h00.

The user sets the phase difference lock window time,

tLWW, for a valid LOCK condition with the LKWIN[1:0]

bits. See Table 3 for recommended settings for different

fPFD frequencies and the Applications Information section

for examples.

Table 3. LKWIN[1:0] Programming

LKWIN[1:0]

tLWW

0

3ns

1

10ns

2

30ns

3

90ns

fPFD

>5MHz

≤5MHz

≤1.7MHz

≤550kHz

The PFD phase difference must be less than tLWW for the

COUNTS number of successive counts before the lock

indicator asserts the LOCK flag. The LKCT[1:0] bits found

in register h09 are used to set COUNTS depending upon

the application. See Table 4 for LKCT[1:0] programming

and the Applications Information section for examples.

Table 4. LKCT[1:0] Programming

LKCT[1:0]

0

1

2

3

COUNTS

32

128

512

2048

When the PFD phase difference is greater than tLWW, the

lock indicator immediately asserts the UNLOCK status

flag and clears the LOCK flag, indicating an out-of-lock

condition. The UNLOCK flag is immediately de-asserted

when the phase difference is less than tLWW. See Figure 4

for more details.

+tLWW

PHASE

DIFFERENCE 0

AT PFD

–tLWW

UNLOCK FLAG

LOCK FLAG

t = COUNTS/fPFD

6945 F04

Figure 4. UNLOCK and LOCK Timing

6945f

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