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LTC693I

Microprocessor Supervisory Circuits

Linear Technology 

LTC692/LTC693

APPLICATI S I FOR ATIO

The LTC693 provides an additional output (Watchdog

Output, WDO) which goes low if the watchdog timer is

allowed to time out and remains low until set high by the

next transition on the WDI pin. WDO is also set high when

VCC falls below the reset voltage threshold or VBATT.

The LTC693 has two additonal pins OSC SEL and OSC IN,

which allow reset active time and watchdog time-out

period to be adjusted per Table 2. Several configurations

are shown in Figure 12.

OSC IN can be driven by an external clock signal or an

external capacitor can be connected between OSC IN and

GND when OSC SEL is forced low. In these configurations,

the nominal reset active time and watchdog time-out

period are determined by the number of clocks or set by

the formula in Table 2. When OSC SEL is high or floating,

the internal oscillator is enabled and the reset active time

is fixed at 140ms minimum. OSC IN selects between the

1 second and 70ms minimum normal watchdog time-out

periods. In both cases, the time-out period immediately

after a reset is at least 1 second.

VCC = 5V

WDI

WDO

RESET

t1 = RESET ACTIVE TIME

t2 = NORMAL WATCHDOG TIME-OUT PERIOD

t3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY

AFTER A RESET

t2

t3

t1

t1

Figure 11. Watchdog Time-out Period and Reset Active Time

EXTERNAL CLOCK

3

5V

VCC

8

OSC SEL

LTC693

4

GND

7

OSC IN

EXTERNAL OSCILLATOR

5V 3 VCC

8

OSC SEL

LTC693

4

GND

7

OSC IN

LTC692/3 • F11

INTERNAL OSCILLATOR

1.6 SECOND WATCHDOG

3

5V

VCC

8

OSC SEL

FLOATING

OR HIGH

LTC693

4

GND

7 FLOATING

OSC IN

OR HIGH

INTERNAL OSCILLATOR

100ms WATCHDOG

3

5V

VCC

8 FLOATING

OSC SEL

OR HIGH

LTC693

4

GND

7

OSC IN

Figure 12. Oscillator Configurations

LTC692/3 • F12

13

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