LTC4101EG Просмотр технического описания (PDF) - Linear Technology

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LTC4101EG

Smart Battery Charger Controller

Linear Technology 

LTC4101

OPERATION

The Voltage DAC Block

Note that the charger output voltage is offset by VREF.

Therefore, the value of VREF is subtracted from the SMBus

ChargingVoltage() value in order for the output voltage to

be programmed properly (without offset). If the Charging-

Voltage() value is below the nominal reference voltage of

the charger, nominally 1.104V, the charger output voltage

is programmed to zero. In addition, if the ChargingVolt-

age() value is above the limit set by the VLIM pin, then the

charger output voltage is set to the value determined by

the VLIM resistor and the VOLTAGE_OR bit is set. These

limits are demonstrated in Figure 6.

6

RVLIM = 33k

5

4

3

2

1

0

0

1

2

34

5

6

PROGRAMMED VALUE (V)

4101 F06

NOTE: THE LTC4101 CAN BE PROGRAMMED WITH ChargingVoltage() FUNCTION VALUES

BETWEEN 1.104V AND 2.9V, HOWEVER, THE BATTERY CHARGER CONTROLLER OUTPUT

VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2.9V.

Figure 6. Transfer Function of Charger

The Current DAC Block

The current DAC is a delta-sigma modulator which controls

the effective value of an external resistor, RSET, used to

set the current limit of the charger. Figure 7 is a simplified

diagram of the DAC operation. The delta-sigma modulator

and switch convert the ChargingCurrent() value, received

via the SMBus, to a variable resistance equal to:

1.25RSET/[ChargingCurrent()/ILIM[x]] = RIDC

Therefore, programmed current is equal to:

ICHARGE = (102.3mV/RSENSE) (ChargingCurrent()/ILIM[x]),

for ChargingCurrent() < ILIM[x].

20

IDC

20

IPROG

(FROM CA1 AMP)

–

RSET

VREF +

Δ-∑

MODULATOR

ITH

19

CHARGING_CURRENT

VALUE

4101 F07

Figure 7. Current DAC Operation

When a value less than 1/16th of the maximum current

allowed by ILIM is applied to the current DAC input, the

current DAC enters a different mode of operation called

LOWI. The current DAC output is pulse width modulated

with a high frequency clock having a duty cycle value of

1/8. Therefore, the maximum output current provided by

the charger is IMAX/8. The delta-sigma output gates this

low duty cycle signal on and off. The delta-sigma shift

registers are then clocked at a slower rate, about 45ms/bit,

so that the charger has time to settle to the IMAX/8 value.

The resulting average charging current is equal to that

requested by the ChargingCurrent() value.

Note: The LOWI mode can be disabled by setting the

NO_LOWI bit in the LTC0() function.

When wake-up is asserted to the current DAC block, the

delta-sigma is then fixed at a value equal to 80mA, inde-

pendent of the ILIM setting.

Input FET

The input FET circuit performs two functions. It enables

the charger if the input voltage is higher than the CLP pin,

and provides an indication of this condition at both the

CHGEN pin and the PWR_FAIL bit in the ChargerStatus()

register. It also controls the gate of the input FET to keep

a low forward voltage drop when charging and prevents

reverse current flow through the input FET.

If the input voltage is less than VCLP, it must go at least

130mV higher than VCLP to activate the charger. The CHGEN

pin is forced low unless this condition is met. The gate

of the input FET is driven to a voltage sufficient to keep

a low forward voltage drop from drain to source. If the

voltage between DCIN and CLP drops to less than 25mV,

the input FET is turned off slowly. If the voltage between

4101fa

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