LTC3561 Просмотр технического описания (PDF) - Linear Technology

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LTC3561

1A, 4MHz, Synchronous Step-Down DC/DC Converter

Linear Technology 

LTC3561

APPLICATIO S I FOR ATIO

For cost reasons, a ceramic capacitor will be used. COUT

selection is then based on load step droop instead of ESR

requirements. For a 5% output droop:

C OUT

≈

2.5

1MHz

1A

• (5%• 2.5V)

=

20µF

The closest standard value is 22µF. Since the output

impedance of a Li-Ion battery is very low, CIN is typically

10µF. In noisy environments, decoupling SVIN from PVIN

with an R6/C8 filter of 1Ω/0.1µF may help, but is typically

not needed.

The output voltage can now be programmed by choosing

the values of R1 and R2. To maintain high efficiency, the

current in these resistors should be kept small. Choosing

2µA with the 0.8V feedback voltage makes R1~400k. A

close standard 1% resistor is 412k and R2 is then 887k.

The compensation should be optimized for these compo-

nents by examining the load step response but a good

place to start for the LTC3561 is with a 13kΩ and 1000pF

filter. The output capacitor may need to be increased

depending on the actual undershoot during a load step.

The circuit in Figure 6 shows the complete schematic for

this design example.

Board Layout Considerations

When laying out the printed circuit board, the follow-

ing checklist should be used to ensure proper oper-

ation of the LTC3561. These items are also illustrated

graphically in the layout diagram of Figure 5. Check

the following in your layout:

1. Does the capacitor CIN connect to the power VIN (Pin 5)

and power GND (Pin 4) as close as possible? This

capacitor provides the AC current to the internal power

MOSFETs and their drivers.

2. Are the COUT and L1 closely connected? The (–) plate of

COUT returns current to PGND and the (–) plate of CIN.

3. The resistor divider, R1 and R2, must be connected

between the (+) plate of COUT and a ground line termi-

nated near SGND (Pin 2). The feedback signal VFB

should be routed away from noisy components and

traces, such as the SW line (Pin 3), and its trace should

be minimized.

4. Keep sensitive components away from the SW pin. The

input capacitor CIN, the compensation capacitor CC and

CITH and all the resistors R1, R2, RT, and RC should be

routed away from the SW trace and the inductor L1.

5. A ground plane is preferred, but if not available, keep the

signal and power grounds segregated with small signal

components returning to the SGND pin at one point

which is then connected to the PGND pin.

6. Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise of

power components. These copper areas should be

connected to one of the input supplies: PVIN, PGND,

SVIN or SGND.

CIN

VIN

PVIN

PGND

L1

SVIN LTC3561 SW

VFB

SGND

C4

R2 R1 R3

ITH

C3

SHDN/RT

RT

BOLD LINES INDICATE HIGH CURRENT PATHS

COUT

VOUT

3561 F06

Figure 5. LTC3561 Layout Diagram (See Board Layout Checklist)

3561f

12

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