LTC3541EDD-3 Просмотр технического описания (PDF) - Linear Technology

Номер в каталоге

Компоненты Описание

производитель

LTC3541EDD-3

High Efficiency Buck + VLDO Regulator

Linear Technology 

LTC3541-3

APPLICATIO S I FOR ATIO

equal to logic high), efficiency is typically dominated by

the loss across the linear regulator output device and VIN

quiescent current. In a typical efficiency plot, the efficiency

curve at very low load currents can be misleading since

the actual power lost is of little consequence.

1. The VIN quiescent current loss in the buck is due to two

components: the DC bias current as given in the Electrical

Characteristics and the internal main switch and synchro-

nous switch gate charge currents. The gate charge current

results from switching the gate capacitance of the internal

power switches. Each time the gate is switched from high

to low to high again, a packet of charge, dQ, moves from

VIN to ground. The resulting dQ/dt is the current out of

VIN that is typically larger than the DC bias current and

proportional to frequency. Both the DC bias and gate charge

losses are proportional to VIN and thus their effects will

be more pronounced at higher supply voltages.

2. I2R losses are calculated from the resistances of the

internal switches, RSW, and external inductor RL. In con-

tinuous mode, the average output current flowing through

inductor L is “chopped” between the main switch and the

synchronous switch. Thus, the series resistance looking

into the SW pin is a function of both top and bottom

MOSFET RDS(ON) and the duty cycle (DC) as follows:

RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs can

be obtained from the Typical Performance Characteristics

curves. Thus, to obtain I2R losses, simply add RSW to

RL and multiply the result by the square of the average

output current.

3. Losses in the VLDO/linear regulator are due to the DC bias

currents as given in the Electrical Characteristics and to the

(VIN – VOUT) voltage drop across the internal output device

transistor.

Other losses when the buck and VLDO regulator are

in operation (ENBUCK and ENVLDO equal logic high),

including CIN and COUT ESR dissipative losses and induc-

tor core losses, generally account for less than 2% total

additional loss.

THERMAL CONSIDERATIONS

The LTC3541-3 requires the package backplane metal

(GND pin) to be well soldered to the PC board. This gives

the DFN package exceptional thermal properties. The

power handling capability of the device will be limited

by the maximum rated junction temperature of 125°C.

The LTC3541-3 has internal thermal limiting designed to

protect the device during momentary overload conditions.

For continuous normal conditions, the maximum junction

temperature rating of 125°C must not be exceeded. It is

important to give careful consideration to all sources of

thermal resistance from junction to ambient. Additional

heat sources mounted nearby must also be considered.

For surface mount devices, heat sinking is accomplished

by using the heat-spreading capabilities of the PC board

and its copper traces. Copper board stiffeners and plated

through holes can also be used to spread the heat gener-

ated by power devices.

To avoid the LTC3541-3 exceeding the maximum junction

temperature, some thermal analysis is required. The goal

of the thermal analysis is to determine whether the power

dissipated exceeds the maximum junction temperature of

the part. The temperature rise is given by:

TR = PD • qJA

where PD is the power dissipated by the regulator and qJA

is the thermal resistance from the junction of the die to

the ambient temperature.

The junction temperature, TJ, is given by:

TJ = TA + TR

where TA is the ambient temperature.

As an example, consider the LTC3541-3 at an input volt-

age VIN of 3V, an LVIN voltage of 1.8V provided by the buck

regulator, an LVOUT voltage of 1.575V, a load current of

300mA for the VLDO regulator, a load current of 200mA

for the buck (total load for buck = 500mA), and an ambient

temperature of 85°C. From the typical performance graph

of switch resistance, the RDS(ON) of the P-channel switch at

35413fc

15

Share Link: