LTC2281 Просмотр технического описания (PDF) - Linear Technology

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LTC2281

Dual 10-Bit, 125Msps Low Power 3V ADC

Linear Technology 

LTC2281

PIN FUNCTIONS

AINA+ (Pin 1): Channel A Positive Differential Analog

Input.

AINA– (Pin 2): Channel A Negative Differential Analog

Input.

REFHA (Pins 3, 4): Channel A High Reference. Short to-

gether and bypass to Pins 5, 6 with a 0.1μF ceramic chip

capacitor as close to the pin as possible. Also bypass to

Pins 5, 6 with an additional 2.2μF ceramic chip capacitor

and to ground with a 1μF ceramic chip capacitor.

REFLA (Pins 5, 6): Channel A Low Reference. Short to-

gether and bypass to Pins 3, 4 with a 0.1μF ceramic chip

capacitor as close to the pin as possible. Also bypass to

Pins 3, 4 with an additional 2.2μF ceramic chip capacitor

and to ground with a 1μF ceramic chip capacitor.

VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to

GND with 0.1μF ceramic chip capacitors.

CLKA (Pin 8): Channel A Clock Input. The input sample

starts on the positive edge.

CLKB (Pin 9): Channel B Clock Input. The input sample

starts on the positive edge.

REFLB (Pins 11, 12): Channel B Low Reference. Short

together and bypass to Pins 13, 14 with a 0.1μF ceramic

chip capacitor as close to the pin as possible. Also by-

pass to Pins 13, 14 with an additional 2.2μF ceramic

chip capacitor and to ground with a 1μF ceramic chip

capacitor.

REFHB (Pins 13, 14): Channel B High Reference. Short

together and bypass to Pins 11, 12 with a 0.1μF ceramic

chip capacitor as close to the pin as possible. Also by-

pass to Pins 11, 12 with an additional 2.2μF ceramic

chip capacitor and to ground with a 1μF ceramic chip

capacitor.

AINB– (Pin 15): Channel B Negative Differential Analog

Input.

AINB+ (Pin 16): Channel B Positive Differential Analog

Input.

GND (Pins 17, 64): ADC Power Ground.

SENSEB (Pin 19): Channel B Reference Programming Pin.

Connecting SENSEB to VCMB selects the internal reference

and a ±0.5V input range. VDD selects the internal reference

8

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEB selects an input

range of ±VSENSEB. ±1V is the largest valid input range.

VCMB (Pin 20): Channel B 1.5V Output and Input Common

Mode Bias. Bypass to ground with 2.2μF ceramic chip

capacitor. Do not connect to VCMA.

MUX (Pin 21): Digital Output Multiplexer Control. If MUX is

High, Channel A comes out on DA0-DA9; Channel B comes

out on DB0-DB9. If MUX is Low, the output busses are

swapped and Channel A comes out on DB0-DB9; Channel

B comes out on DA0-DA9. To multiplex both channels

onto a single output bus, connect MUX, CLKA and CLKB

together. (This is not recommended at clock frequencies

above 80Msps.)

SHDNB (Pin 22): Channel B Shutdown Mode Selection

Pin. Connecting SHDNB to GND and OEB to GND results

in normal operation with the outputs enabled. Connecting

SHDNB to GND and OEB to VDD results in normal operation

with the outputs at high impedance. Connecting SHDNB

to VDD and OEB to GND results in nap mode with the

outputs at high impedance. Connecting SHDNB to VDD

and OEB to VDD results in sleep mode with the outputs

at high impedance.

OEB (Pin 23): Channel B Output Enable Pin. Refer to

SHDNB pin function.

NC (Pins 24 to 27, 41 to 44): Do not connect these

pins.

DB0 – DB9 (Pins 28 to 30, 33 to 39): Channel B Digital

Outputs. DB9 is the MSB.

OGND (Pins 31, 50): Output Driver Ground.

OVDD (Pins 32, 49): Positive Supply for the Output Drivers.

Bypass to ground with 0.1μF ceramic chip capacitor.

CLKOUT (Pin 40): Data Ready Clock Output. Latch data

on the falling edge of CLKOUT. CLKOUT is derived from

CLKB. Tie CLKA to CLKB for simultaneous operation.

DA0 – DA9 (Pins 45 to 48, 51 to 56): Channel A Digital

Outputs. DA9 is the MSB.

OF (Pin 57): Overflow/Underflow Output. High when an

overflow or underflow has occurred on either channel A

or channel B.

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