LTC2281 Просмотр технического описания (PDF) - Linear Technology
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LTC2281 Datasheet PDF : 24 Pages
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LTC2281
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
VDD
OVDD
Analog Supply Voltage
Output Supply Voltage
(Note 9)
(Note 9)
● 2.85 3
3.4
V
● 0.5 3
3.6
V
IVDD
PDISS
PSHDN
PNAP
Supply Current
Power Dissipation
Shutdown Power (Each Channel)
Nap Mode Power (Each Channel)
Both ADCs at fS(MAX)
Both ADCs at fS(MAX)
SHDN = H, OE = H, No CLK
SHDN = H, OE = L, No CLK
●
263 305
mA
●
790 915
mW
2
mW
15
mW
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fs
tL
PARAMETER
Sampling Frequency
CLK Low Time
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
MIN TYP MAX
●
1
125
● 3.8
4
500
●
3
4
500
UNITS
MHz
ns
ns
tH
CLK High Time
Duty Cycle Stabilizer Off (Note 7)
● 3.8
4
500
ns
Duty Cycle Stabilizer On (Note 7)
●
3
4
500
ns
tAP
Sample-and-Hold Aperture Delay
tD
CLK to DATA Delay
CL = 5pF (Note 7)
0
ns
● 1.4 2.7 5.4
ns
tC
CLK to CLKOUT Delay
DATA to CLKOUT Skew
CL = 5pF (Note 7)
(tD – tC) (Note 7)
● 1.4 2.7 5.4
ns
● –0.6
0
0.6
ns
tMD
MUX to DATA Delay
Data Access Time After OE↓
CL = 5pF (Note 7)
CL = 5pF (Note 7)
● 1.4 2.7 5.4
ns
●
4.3 10
ns
BUS Relinquish Time
(Note 7)
●
3.3 8.5
ns
Pipeline Latency
5
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 125MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 and 11 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 125MHz, input range = 1VP-P with differential
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
Note 9: Recommended operating conditions.
2281fb
5
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