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LTC2208IUP-14

14-Bit, 130Msps ADC

Linear Technology 

LTC2208-14

APPLICATIONS INFORMATION

input change is large, such as the change seen with input

frequencies near Nyquist, then a larger charging glitch

will be seen.

Common Mode Bias

The ADC sample-and-hold circuit requires differential

drive to achieve specified performance. Each input should

swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V

for the 1.5V range (PGA = 1), around a common mode

voltage of 1.25V. The VCM output pin (Pin 3) is designed

to provide the common mode bias level. VCM can be tied

directly to the center tap of a transformer to set the DC

input level or as a reference level to an op amp differential

driver circuit. The VCM pin must be bypassed to ground

close to the ADC with 2.2μF or greater.

Input Drive Impedance

As with all high performance, high speed ADCs the dy-

namic performance of the LTC2208-14 can be influenced

by the input drive circuitry, particularly the second and

third harmonics. Source impedance and input reactance

can influence SFDR. At the falling edge of ENC the

sample and hold circuit will connect the 4.9pF sampling

capacitor to the input pin and start the sampling period.

The sampling period ends when ENC rises, holding the

sampled input on the sampling capacitor. Ideally, the

input circuitry should be fast enough to fully charge

the sampling capacitor during the sampling period

1/(2F encode); however, this is not always possible and the

incomplete settling may degrade the SFDR. The sampling

glitch has been designed to be as linear as possible to

minimize the effects of incomplete settling.

For the best performance it is recommended to have a

source impedance of 100Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

INPUT DRIVE CIRCUITS

Input Filtering

A first order RC low pass filter at the input of the ADC can

serve two functions: limit the noise from input circuitry and

provide isolation from ADC S/H switching. The LTC2208-14

has a very broadband S/H circuit, DC to 700MHz; it can

be used in a wide range of applications; therefore, it is not

possible to provide a single recommended RC filter.

Figures 3, 4a and 4b show three examples of input RC

filtering at three ranges of input frequencies. In general

it is desirable to make the capacitors as large as can be

tolerated—this will help suppress random noise as well

as noise coupled from the digital circuitry. The LTC2208-

14 does not require any input filter to achieve data sheet

specifications; however, no filtering will put more stringent

noise requirements on the input drive circuitry.

Transformer Coupled Circuits

Figure 3 shows the LTC2208-14 being driven by an RF

transformer with a center-tapped secondary. The secondary

center tap is DC biased with VCM, setting the ADC input

signal at its optimum DC level. Figure 3 shows a 1:1 turns

ratio transformer. Other turns ratios can be used; however,

as the turns ratio increases so does the impedance seen by

the ADC. Source impedance greater than 50Ω can reduce

the input bandwidth and increase high frequency distor-

tion. A disadvantage of using a transformer is the loss of

low frequency response. Most small RF transformers have

poor performance at frequencies below 1MHz.

Center-tapped transformers provide a convenient means

of DC biasing the secondary; however, they often show

poor balance at high input frequencies, resulting in large

2nd order harmonics.

VCM

5Ω

10Ω

T1

0.1μF

10Ω

2.2μF

5Ω AIN+

8.2pF

35Ω

8.2pF

LTC2208-14

35Ω

5Ω AIN–

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

EXCEPT 2.2μF

8.2pF

220814 F03

Figure 3. Single-Ended to Differential Conversion

Using a Transformer. Recommended for Input

Frequencies from 5MHz to 100MHz

220814fb

19

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