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LT3745EUJ

16-Channel 50mA LED Driver with Buck Controller

Linear Technology 

LT3745

Operation

The LT3745 integrates a single constant-frequency current-

mode nonsynchronous buck controller with sixteen linear

current sinks. The buck controller generates an adaptive

output LED bus voltage to supply parallel LED strings and

the sixteen linear current sinks regulate and modulate

individual LED strings. Its operation is best understood

by referring to the Block Diagram.

Start-Up

The LT3745 enters shutdown mode and drains almost zero

current when the EN/UVLO pin is lower than 0.35V. Once

the EN/UVLO pin is above 0.35V, the part starts to wake

up internal bias currents, generate various references,

and charge the capacitor CCAP towards 6.8V regulation

voltage. This VIN referenced voltage regulator (VIN - VCAP)

will supply the internal gate driver circuitry driving an

external P-channel MOSFET in normal operation. The

LT3745 remains in undervoltage lockout (UVLO) mode

as long as any one of the EN/UVLO, VCC, and (VIN - VCAP)

UVLO flags is high. Their UVLO thresholds are typically

1.31V, 2.89V, and 4.9V, respectively. After all the UVLO

flags are cleared, the buck controller starts to switch, and

the soft-start SS pin is released and charged by a 12µA

current source, thereby smoothly ramping up the inductor

current and the output LED bus voltage.

Power-on-Reset (POR)

During start-up, an internal power-on-reset (POR) high

signal blocks the input signals to the serial data interface

and resets all the internal registers except the 194-bit shift

register. The 1-bit frame select (FS) register, 1-bit enable

LED channel (EN) register, individual 12-bit grayscale (GS)

registers, and individual 6-bit dot correction (DC) registers

are all reset to zero. Thus all the LED channels are turned off

initially with the default grayscale (0x000) and dot correc-

tion (0x00) setting. Once the part completes its soft-start

(i.e., the SS pin voltage is higher than 1V) and the output

LED bus voltage is power good (i.e., within 5% of its FB

programmed regulation level), the POR signal goes low

to allow the input signals to the serial data interface. Any

fault triggering the soft-start will generate another POR

high signal and reset internal registers again.

Serial Data Interface

The LT3745 has a 30MHz, fully-buffered, skew-balanced,

cascadable serial data interface. The interface uses a novel

6-wire (LDI, SCKI, SDI, LDO, SCKO, and SDO) topology

and can be connected to microcontrollers, digital signal

processors (DSPs), or field programmable gate arrays

(FPGAs).

In a conventional 4-wire topology shown in Figure 1, the LDI

and SCKI signals need global routing while the SDI signal

only needs local routing between chips. Depending on the

number of chips in cascade and the size of system PCB

board, external clock-tree type buffers with corresponding

driving capability are needed for both the LDI and SCKI

signals to minimize signal skews. The propagation delay

caused by the buffer insertion on the SCKI signal yields

LDO

SCKO

SDO

CONTROLLER

SDI

SCKI

LDI

LT3745 6-WIRE TOPOLOGY

LDI CHIP 1 LDO

SCKI

SCKO

SDI

SDO

LDI CHIP 2 LDO

SCKI

SCKO

SDI

SDO

CONVENTIONAL 4-WIRE TOPOLOGY

LDI CHIP N LDO

SCKI

SCKO

SDI

SDO

LDO

SCKO

SDO

CONTROLLER

SDI

LDI CHIP 1 LDO

SCKI

SCKO

SDI

SDO

LDI CHIP 2 LDO

SCKI

SCKO

SDI

SDO

LDI CHIP N LDO

SCKI

SCKO

SDI

SDO

3745 F01

Figure 1. LT3745 6-Wire Topology vs Conventional 4-Wire Topology

3745f

13

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