LT3579IUFD-1-PBF Просмотр технического описания (PDF) - Linear Technology

Номер в каталоге

Компоненты Описание

производитель

LT3579IUFD-1-PBF

6A Boost/Inverting DC/DC Converter with Fault Protection

Linear Technology 

LT3579/LT3579-1

APPENDIX

Table 6 shows a list of several ceramic capacitor man-

ufacturers. Consult the manufacturers for detailed infor-

mation on their entire selection of ceramic parts.

Table 6. Ceramic Capacitor Manufacturers

TDK

www.tdk.com

Murata

www.murata.com

Taiyo Yuden

www.t-yuden.com

PMOS SELECTION

An external PMOS, controlled by the LT3579’s GATE pin,

can be used to facilitate input or output disconnect. The

GATE pin turns on the PMOS gradually during start-up

(see Soft-Start of External PMOS in the Operation section),

and turns the PMOS off when the LT3579 is in shutdown

or in fault.

The use of the external PMOS, controlled by the GATE pin,

is particularly beneficial when dealing with unintended

output shorts in a boost regulator. In a conventional boost

regulator, the inductor, Schottky diode, and power switches

are susceptible to damage in the event of an output short

to ground. Using an external PMOS in the boost regulator’s

power path (path from VIN to VOUT) controlled by the GATE

pin, will serve to disconnect the input from the output

when the output has a short to ground, thereby helping

save the IC, and the other components in the power path

from damage.

The PMOS chosen must be capable of handling the

maximum input or output current depending on whether

the PMOS is used at the input (see Figure 12) or the output

(see Figure 13).

Ensure that the PMOS is biased with enough source to gate

voltage (VSG) to enhance the device into the triode mode

of operation. The higher the VSG voltage that biases the

PMOS, the lower the RDSON of the PMOS, thereby lowering

power dissipation in the device during normal operation,

as well as improving the efficiency of the application in

which the PMOS is used. The following equations show

the relationship between RGATE (see Block Diagram) and

the desired VSG that the PMOS is biased with:

VSG

=

⎧

⎨⎪VS

RGATE

RGATE + 2kΩ

⎪

⎩

933μA •RGATE

if

if

VGATE

VGATE

< 2V

> 2V

When using a PMOS, it is advisable to configure the specific

application for undervoltage lockout (see the Operations

section). The goal is to have VIN get to a certain minimum

voltage where the PMOS has sufficient headroom to attain

a high enough VSG, which prevents it from entering the

saturation mode of operation during start-up.

Figure 6 shows the PMOS connected in series with the

output to act as an output disconnect during a fault

condition. The Schottky diode from the VIN pin to the GATE

pin is optional and helps turn off the PMOS quicker in the

event of hard shorts. The resistor from VIN to the SHDN

pin sets a UVLO of 4V for this application.

Connecting the PMOS in series with the output offers certain

advantages over connecting it in series with the input:

• Since the load current is always less than the input

current for a boost converter, the current rating of the

PMOS goes down when connected in series with the

output as opposed to the input.

• A PMOS in series with the output can be biased with

a higher overdrive voltage than a PMOS used in series

with the input, since VOUT > VIN. This higher overdrive

results in a lower RDSON for the PMOS, thereby improving

the efficiency of the regulator.

In contrast, an input connected PMOS works as a simple

hot-plug controller (covered in more detail in the Hot-Plug

section). The input connected PMOS also functions as an

inexpensive means of protecting against multiple output

shorts in boost applications that synchronize the LT3579

with other compatible ICs (see Figure 12).

35791f

27

Share Link: