LT3570 Просмотр технического описания (PDF) - Linear Technology
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LT3570 Datasheet PDF : 20 Pages
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LT3570
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
4.50 ± 0.05
2.45 ± 0.05
3.10 ± 0.05 (4 SIDES)
0.70 ±0.05
4.00 ± 0.10
(4 SIDES)
PIN 1
TOP MARK
(NOTE 6)
0.75 ± 0.05
2.45 ± 0.10
(4-SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
23 24
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.40 ± 0.10
1
2
PACKAGE
OUTLINE
(UF24) QFN 0105
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
3.86
(.152)
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
4.50 ±0.10
SEE NOTE 4
2.74
(.108)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.25
REF 0° – 8°
2.74
(.108)
6.40
(.252)
BSC
1 2 3 4 5 6 7 8 9 10
1.20
(.047)
MAX
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2.
DIMENSIONS
ARE
IN
MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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