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LT3435(RevA) Просмотр технического описания (PDF) - Linear Technology

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LT3435 Datasheet PDF : 24 Pages
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LT3435
TYPICAL PERFOR A CE CHARACTERISTICS
Dropout Operation
4.0 VOUT = 3.3V
3.5 BOOST DIODE = DIODES INC DFLS160
3.0
2.5
2.0
1.5
LOAD CURRENT = 2.5A
1.0
LOAD CURRENT = 250mA
0.5
0
2 2.5 3 3.5 4 4.5 5 5.5 6
INPUT VOLTAGE (V)
3435 G19
Burst Mode Operation
Dropout Operation
6
VOUT = 5V
BOOST DIODE = DIODES INC DFLS160
5
4
Burst Mode Operation
VOUT
50mV/DIV
AC-COUPLED
3
ISW
500mA/DIV
LOAD CURRENT = 2.5A
2
1
LOAD CURRENT = 250mA
VIN = 12V
VOUT = 3.3V
10ms/DIV
0
2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
INPUT VOLTAGE (V)
3435 G20
No Load 2A Step Response
Step Response
VOUT
50mV/DIV
AC-COUPLED
VOUT
200mV/DIV
AC-COUPLED
VOUT
200mV/DIV
AC-COUPLED
ISW
500mA/DIV
VIN = 12V
VOUT = 3.3V
10µs/DIV
3435 G22
IOUT
1A/DIV
VIN = 12V
VOUT = 3.3V
COUT = 100µF
500µs/DIV
IOUT
1A/DIV
3435 G23
VIN = 12V
500µs/DIV
VOUT = 3.3V
COUT = 100µF
ILOAD(DC) = 500mA
3435 G21
3435 G24
PI FU CTIO S
NC (Pin 1): No Connection.
SW (Pins 2, 5): The SW pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
SW pin negative during switch off time. Negative voltage
is clamped with the external catch diode. Maximum nega-
tive switch voltage allowed is –0.8V.
VIN (Pins 3, 4): This is the collector of the on-chip power
NPN switch. VIN powers the internal control circuitry when
a voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
6
inductance on this path will create a voltage spike at switch
off, adding to the VCE voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.1FET
structure.
CT (Pin 7): A capacitor on the CT pin determines the amount
of delay time between the PGFB pin exceeding its thresh-
old (VPGFB) and the PG pin set to a high impedance state.
3435fa

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