LT1469CN8(RevA) Просмотр технического описания (PDF) - Linear Technology
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LT1469CN8 Datasheet PDF : 20 Pages
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LT1469
APPLICATIONS INFORMATION
the amplifier. Air currents over device leads should be
minimized, package leads should be short and the two
input leads should be as close together as possible and
maintained at the same temperature.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with the
input capacitance to form a pole which can cause peaking
or even oscillations. For feedback resistors greater than
2k, a feedback capacitor of value CF > RG • CIN/RF should
be used to cancel the input pole and optimize dynamic
performance. For applications where the DC noise gain is
one, and a large feedback resistor is used, CF should be
greater than or equal to CIN. An example would be a DAC
I-to-V converter as shown on the front page of the data
sheet where the DAC can have many tens of picofarads
of output capacitance. Another example would be a gain
of –1 with 5k resistors; a 5pF to 10pF capacitor should
be added across the feedback resistor.
Input Considerations
Each input of the LT1469 is protected with a 100Ω series
resistor and back-to-back diodes across the bases of
the input devices. If large differential input voltages are
anticipated, limit the input current to less than 10mA with
an external series resistor. Each input also has two ESD
clamp diodes—one to each supply. If an input is driven
beyond the supply, limit the current with an external resis-
tor to less than 10mA.
CF
The LT1469 employs bias current cancellation at the inputs.
The inverting input current is trimmed at zero common
mode voltage to minimize errors in inverting applications
such as I-to-V converters. The noninverting input current
is not trimmed and has a wider variation and therefore a
larger maximum value. As the input offset current can be
greater than either input current, the use of balanced source
resistance is NOT recommended as it actually degrades
DC accuracy and also increases noise.
The input bias currents vary with common mode voltage.
The cancellation circuitry was not designed to track this
common mode voltage because the settling time would
have been adversely affected.
The LT1469 inputs can be driven to the negative supply
and to within 0.5V of the positive supply without phase
reversal. As the input moves closer than 0.5V to the posi-
tive supply, the output reverses phase.
Total Input Noise
The total input noise of the LT1469 is optimized for a source
resistance between 1k and 20k. Within this range, the
total input noise is dominated by the noise of the source
resistance itself. When the source resistance is below
1k, voltage noise of the amplifier dominates. When the
source resistance is above 20k, the input noise current is
the dominant contributor.
V+
RG
RF
–
CIN 1/2 LT1469
VIN
+
VOUT
1469 F01
Figure 1. Nulling Input Capacitance
R1
100Ω Q1
+IN
R1
Q2 100Ω
–IN
V–
1469 F02
Figure 2. Input Stage Protection
1469fa
12
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