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LQFP100

Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC

NXP Semiconductors. 

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

Table 4. Pin description …continued

Symbol

Pin

Ball

Type

P2[12]/EINT2/ 51[6]

MCIDAT2/

I2STX_WS

K10[6] I/O

I

O

I/O

P2[13]/EINT3/ 50[6]

J9[6]

I/O

MCIDAT3/

I

I2STX_SDA

O

I/O

P3[0] to P3[31]

I/O

P3[25]/MAT0[0]/ 27[1]

H3[1]

I/O

PWM1[2]

O

O

P3[26]/MAT0[1]/ 26[1]

K1[1]

I/O

PWM1[3]

O

O

P4[0] to P4[31]

I/O

P4[28]/MAT2[0]/ 82[1]

TXD3

P4[29]/MAT2[1]/ 85[1]

RXD3

DBGEN

-

C7[1]

I/O

O

O

E6[1]

I/O

O

I

D4[1][8] I

TDO

TDI

TMS

TRST

TCK

RTCK

1[1][7]

2[1][8]

3[1][8]

4[1][8]

5[1][7]

A1[1][7] O

C3[1][8] I

B1[1][8] I

C2[1][8] I

C1[1][7] I

100[1][8] B2[1][8] I/O

Description

P2[12] — General purpose digital input/output pin.

EINT2 — External interrupt 2 input.

MCIDAT2 — Data line for SD/MMC interface. (LPC2367/68 only)

I2STX_WS — Transmit Word Select. It is driven by the master and

received by the slave. Corresponds to the signal WS in the I2S-bus

specification.

P2[13] — General purpose digital input/output pin.

EINT3 — External interrupt 3 input.

MCIDAT3 — Data line for SD/MMC interface. (LPC2367/68 only)

I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I2S-bus specification.

Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each

bit. The operation of Port 3 pins depends upon the pin function selected via

the pin connect block. Pins 0 through 24, and 27 through 31 of this port are

not available.

P3[25] — General purpose digital input/output pin.

MAT0[0] — Match output for Timer 0, channel 0.

PWM1[2] — Pulse Width Modulator 1, output 2.

P3[26] — General purpose digital input/output pin.

MAT0[1] — Match output for Timer 0, channel 1.

PWM1[3] — Pulse Width Modulator 1, output 3.

Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each

bit. The operation of Port 4 pins depends upon the pin function selected via

the pin connect block. Pins 0 through 27, 30, and 31 of this port are not

available.

P4[28] — General purpose digital input/output pin.

MAT2[0] — Match output for Timer 2, channel 0.

TXD3 — Transmitter output for UART3.

P4[29] — General purpose digital input/output pin.

MAT2[1] — Match output for Timer 2, channel 1.

RXD3 — Receiver input for UART3.

DBGEN — JTAG interface control signal. Also used for boundary scanning.

Note: This pin is available in LPC2364FET100 and LPC2368FET100

devices only (TFBGA package).

TDO — Test Data out for JTAG interface.

TDI — Test Data in for JTAG interface.

TMS — Test Mode Select for JTAG interface.

TRST — Test Reset for JTAG interface.

TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of

the CPU clock (CCLK) for the JTAG interface to operate

RTCK — JTAG interface control signal.

Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to

operate as trace port after reset.

LPC2364_65_66_67_68

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7.1 — 16 October 2013

© NXP B.V. 2013. All rights reserved.

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