LQFP48 Просмотр технического описания (PDF) - STMicroelectronics

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LQFP48

Low-density access line, ARM-based 32-bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces

STMicroelectronics 

STM32F101x4, STM32F101x6

Description

Figure 2. Clock tree

OSC_OUT

OSC_IN

OSC32_IN

OSC32_OUT

MCO

8 MHz

HSI RC

HSI

/2

PLLSRC PLLMUL

..., x16

x2, x3, x4

PLL

SW

HSI

PLLCLK

HSE

SYSCLK AHB

36 MHz

max

Prescaler

/1, 2..512

4-16 MHz

HSE OSC

PLLXTPRE

/2

CSS

36 MHz max

Clock

Enable (3 bits)

/8

HCLK

to AHB bus, core,

memory and DMA

to Cortex System timer

APB1

Prescaler

/1, 2, 4, 8, 16

FCLK Cortex

free running clock

36 MHz max

PCLK1

to APB1

Peripheral Clock peripherals

Enable (13 bits)

TIM2, TIM3

to TIM2, TIM3

If (APB1 prescaler =1) x1

TIMXCLK

else

x2 Peripheral Clock

Enable (3 bits)

APB2

Prescaler

/1, 2, 4, 8, 16

36 MHz max

PCLK2

to APB2

Peripheral Clock peripherals

Enable (11 bits)

LSE OSC

32.768 kHz

/128

LSE

to RTC

RTCCLK

ADC

Prescaler

/2, 4, 6, 8

to ADC

ADCCLK

RTCSEL[1:0]

LSI RC

40 kHz

LSI

to Independent Watchdog (IWDG)

IWDGCLK

Main

/2

Clock Output

MCO

PLLCLK

HSI

HSE

SYSCLK

Legend:

HSE = high-speed external clock signal

HSI = high-speed internal clock signal

LSI = low-speed internal clock signal

LSE = low-speed external clock signal

ai15174

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is

36 MHz.

2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.

Doc ID 15058 Rev 5

13/79

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