LPC2114 Просмотр технического описания (PDF) - NXP Semiconductors.

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LPC2114

Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP flash with 10-bit ADC

NXP Semiconductors. 

NXP Semiconductors

LPC2114/2124

Single-chip 16/32-bit microcontrollers

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufficient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.17.4 Code security (Code Read Protection - CRP)

This feature of the LPC2114/2124/01 allows the user to enable different levels of security

in the system so that access to the on-chip flash and use of the JTAG and ISP can be

restricted. When needed, CRP is invoked by programming a specific pattern into a

dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and flash field updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full flash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too.

It is up to the user’s application to provide (if needed) flash update mechanism using IAP

calls or call reinvoke ISP command to enable flash update via UART0.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Remark: Devices without the suffix /00 or /01 have only a security level equivalent to

CRP2 available.

6.17.5 External interrupt inputs

The LPC2114/2124 include up to nine edge or level sensitive External Interrupt Inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four independent interrupt signals. The External Interrupt Inputs can optionally be used

to wake up the processor from Power-down mode.

6.17.6 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

flash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

LPC2114_2124

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 10 June 2011

© NXP B.V. 2011. All rights reserved.

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