LH79524 Просмотр технического описания (PDF) - NXP Semiconductors.

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Компоненты Описание

производитель

LH79524

System-on-Chip

NXP Semiconductors. 

LH79524/LH79525

NXP Semiconductors

Table 9. LH79525 LCD Data Multiplexing

PIN NO.

157

158

159

PIN NAME

LCDVD2

LCDVD1

LCDVD0

STN MONO 4-BIT

SINGLE PANEL DUAL PANEL

MUSTN3

MUSTN2

MUSTN3

MUSTN2

System-on-Chip

LCD

TOUCH SCREEN

WIRELESS

ROUTER/

SWITCHER

ETHERNET

TRANSCEIVER

ETHERNET

MAC

STN / TFT,

AD-TFT

A/D

UART

CODEC

I2S

LH79524 / LH79525

A/D

SENSOR

ARRAY

UART

USB

GPIO

123

456

789

*0#

KEY

MATRIX

SSP

SERIAL

EEPROM

FLASH

SRAM or

SDRAM

BOOT

ROM

Figure 4. LH79524/LH79525 Application Diagram Example

LH79525-19A

SYSTEM DESCRIPTIONS

ARM720T Processor

The LH79524/LH79525 microcontrollers feature

the ARM720T cached core with an Advanced High-Per-

formance Bus (AHB) interface. The ARM720T features:

• 32-bit ARM720T RISC Core

• 8 kB Cache

• MMU (Windows CE enabled)

The core processor for both is a member of the

ARM7T family of processors. For more information, see

the ARM document, ‘ARM720T (Rev 3) Technical

Reference Manual’, available on ARM’s website at

www.ARM.com.

The LH79524/LH79525 MMU allows mapping Phys-

ical Memory (PA) addresses to virtual memory

addresses. This allows physical memory, which is

constrained by hardware to specific addresses, to be

reorganized at addresses identified by the user. These

user identified locations are called Virtual Addresses

(VA). When the MMU is enabled, Code and Data must

be built, loaded, and executed using Virtual Addresses

which the MMU translates to Physical Addresses. In

addition, the user may implement a memory protection

scheme by using the features of the MMU. Address

translation and memory protection services provided

by the MMU are controlled by the user. The MMU

is directly controlled through the System Control

Coprocessor, Coprocessor 15 (CP15). The MMU is

indirectly controlled by a Translation Table (TT) and

Page Tables (PT) prepared by the user and estab-

lished using a portion of physical memory dedicated by

the user to storing the TT and PT’s.

20

Rev. 02 — 17 March 2009

Product data sheet

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