LH79524 Просмотр технического описания (PDF) - NXP Semiconductors.
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LH79524 Datasheet PDF : 62 Pages
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System-on-Chip
NXP Semiconductors
LH79524/LH79525
PIN NO. SIGNAL NAME
80 A0
79 A1
78 A2
77 A3
76 A4
74 A5
73 A6
72 A7
71 A8
70 A9
69 A10
67 A11
65 A12
63 A13
62 A14
61 A15
99 D0
98 D1
97 D2
96 D3
95 D4
94 D5
93 D6
91 D7
117 SDCLK
116 SDCKE
119 DQM0
118 DQM1
115 nDCS0
114 nDCS1
113 nRAS
112 nCAS
104 nCS0/PM0
103 nCS1/PM1
102 nCS2/PM2
100 nCS3/PM3
110 nBLE0/PM4
109 nBLE1/PM5
106 nOE
111 nWE
130 USBDN
131 USBDP
11 AN0/UL/X+
14 AN1/UR/X–
17 AN2/LL/Y+/PJ3
Table 5. LH79525 Pin Descriptions
TYPE
DESCRIPTION
O External Address Bus
I/O External Data Bus
O SDRAM Clock
O SDRAM Clock Enable
O Data Mask Output to SDRAMs
O SDRAM Chip Select
O SDRAM Chip Select
O Row Address Strobe
O Column Address Strobe
O Static Memory Chip Select; multiplexed with GPO Port M[3:0]
O
Static Memory Byte Lane Enable / Byte Write Enable; multiplexed with
GPIO Port M[5:4]
O Static Memory Output Enable
O Static Memory Write Enable
I/O USB Data Negative (Differential Pair output, single ended and Differential input)
I/O USB Data Positive (Differential Pair output, single ended and Differential input)
I ADC Input 0, 4 wire touch screen Upper Left, 5 wire touch screen X+
I ADC Input 1, 4 wire touch screen Upper Right, 5 wire touch screen X–
I
ADC Input 2, 4 wire touch screen Lower Left, 5 wire touch screen Y+; multiplexed with
GPIO Port J3 (input only)
Product data sheet
Rev. 02 — 17 March 2009
13
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