LC651431N Просмотр технического описания (PDF) - SANYO -> Panasonic
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LC651431N Datasheet PDF : 39 Pages
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LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Parameter
Pulse output
Period
High-level pulse width
Low-level pulse width
Symbol
Conditions
Applicable pins
• See figure 7
tPCY
PE0
• TCYC = 4 × <system clock
period>
tPH
• With external 1 kΩ
PE0
resistors and external 50
pF capacitors on the n-
tPL
channel open-drain outputs PE0
only.
Ratings
Unit
min
typ
max
64 ×
µs
TCYC
32 ×
µs
TCYC
±10%
32 ×
µs
TCYC
±10%
Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 3 and the recommended circuit
constants.
2. The average over a 100 ms period.
3. Applications must hold the operating supply voltage VDD level from the point a HALT instruction is executed until the IC enters the standby state.
Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle.
4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo
specified oscillator characteristics evaluation board.
5. The OSC1 pin has Schmitt trigger characteristics when either 2-pin RC oscillator or external clock input is specified as the oscillator option.
6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current
due to the IC output transistors and pull-up resistor transistors is not included.
7. Indicates the frequency when fCFOSC is due to the use of the recommended circuit constants in table 1.
8. Indicates the required time for oscillation to stabilize starting from the point when VDD first exceeds the lower limit of the operating supply voltage
range. (See figure 4.)
9. TCYC = 4 × <system clock period>
No. 6498-16/39
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