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LA4425PV Просмотр технического описания (PDF) - SANYO -> Panasonic

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LA4425PV Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
LA4425PV
IC Usage Notes
Maximum ratings
If the IC is used in the vicinity of the maximum ratings, even a slight variation in conditions may cause the maximum
ratings to be exceeded, thereby leading to a breakdown.
Printed circuit board
When drawing the printed circuit pattern, refer to the sample printed circuit pattern. Be careful not to form a feedback
loop between input and output.
Always use both pins of the Pre GND, Power GND, OUT and VCC when designing the layout.
Exposed Die-Pad
The exposed die pad on the back side of the IC must be connected to GND with a large pattern surface area.
Load Resistance and Misoperation
It should be noted that when RL < 2Ω and VCC is high, and the switch is turned “ON” when setting is for a signal (THD
= 10%), the ground detector (current × voltage Schmitt circuit) operates momentarily.
Starting Time (ts)
This is set at 0.35sec/typ, but it can be made shorter by making input capacitor Ci smaller, or longer by making it larger.
Pop noise
The pop noise prevention circuit operates to reduce pop until Rg reaches 50kΩ. However, if Rg is left open, the charging
route of input capacitor Ci is lost, so the pop noise reduction circuit stops operating and click noises become louder.
VG/OSC
The voltage gain is fixed at 45dB inside the IC. It is impossible to change it externally.
Phase compensation capacitors (350pF/total) are connected between individual stages inside the IC, and the open loop
gain is low. In addition, the upper and lower drives are made equivalent so that final stage current gain is adjusted,
providing a measure against unwanted high-frequency parasitic oscillation peculiar to power IC’s.
BTL Connection
Connection is impossible with IC alone.
PS No.A2011-5/8

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