L6611 Просмотр технического описания (PDF) - STMicroelectronics
Номер в каталоге
Компоненты Описание
производитель
L6611 Datasheet PDF : 28 Pages
| |||
L6611
4 UNDERVOLTAGE, OVERVOLTAGE, DETECTION AND RELEVANT TIMINGS
The IC provides on-board undervoltage and overvoltage protection for 3V3, ±5V, ±12V Main input pins and
Dmon auxiliary input pin. Overcurrent protection is available for 12V and 5V or 3.3V, digitally selectable. The
internal fault logic is illustrated in figure 19.
Figure 19. Simplified Fault logic
Main_OV
+/-12V_Main_UV
+3V3 +5V_Main_UV
ACsense
+
Vref
Debounce 6µs
In
Clock
Out
Reset
Reset
Debounce 6µs
In
Clock
Out
Reset
Reset
Debounce 500µs
In
Clock
Out
Reset
Vdd
UVB 64ms
Reset
In
Clock
Out
Reset
S
Q
Latch
R
Mfault
Dmon_OV
Dmon_UV
Vdd_OV
Vdd_UVL
Restart Mode
Debounce 500µs
In
Clock
Out
Reset
Reset
Reset
Vdd
PS-ON
Debounce 75ms
ON
In
Out
Clock
Reset
Debounce 6µs
In
Clock
Out
Reset
Reset
S
Q
Latch
Reset
R
Vdd
UVB 64ms
In
Clock
Out
Reset D_UVB
Reset
Delay 1s
In
Clock
Out
Reset
S
Q
Latch
R
Reset
Delay 2.5ms
In
Clock
Out
Reset
Reset
S
Q
Latch
Reset
R
Vdd
Delay 250ms
In
Clock
Out
Reset
Vdd
Dfault
Cout
Vdd
PW-OK
– Main inputs overvoltage: whenever one of main outputs (3.3V, +5V, ±12V) is detected as going over-
voltage, MFAULT is latched high (which stops the Main PWM) and PW-OK goes low. Cycling the PS-
ON switch or reducing Vdd below its undervoltage threshold releases the latch. A delay of 6µs is imple-
mented before MFAULT latching.
The OV protection for the 12V and 5V outputs can be disabled (see "On board trimming and mode op-
erating" section).
– Main inputs undervoltage: when an undervoltage on main outputs is detected, MFAULT is latched
high (the Main PWM stops) and PW-OK goes low. The latches are released, by default, cycling the PS-
ON switch or reducing Vdd below its undervoltage threshold (latching mode); optionally, an attempt is
made to restart the supply after of 1 second (bounce mode). The choice depends on the selected mode
(see "On board trimming and mode operating" section).
Debounce logic is implemented for 3.3V and 5V so that an undervoltage condition on these signals has
to last 450µs to be recognized as valid while 6µs debounce logic is implemented for 12V and -12V input
signal. When all main undervoltages are over and ACsns is OK (see the relevant section), PW_OK goes
high after a delay of 250ms.
– Dmon input overvoltage: whenever the Dmon input pin is detected as going overvoltage, both
MFAULT and DFAULT are latched high. The latch is released by reducing Vdd below its undervoltage
threshold. Debounce logic is implemented so that MFAULT and DFAULT signals are latched only if the
overvoltage condition lasts more than 6µs.
To protect the load against overvoltage, typical solutions make use of a power crowbar (SCR) driven by
21/28
Share Link: 