L5953 Просмотр технического описания (PDF) - STMicroelectronics

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L5953

Multiple switching voltage regulator

STMicroelectronics 

L5953

Figure 4. SPI clocking scheme

S

(MODE 0: CPOL=0,CPHA=0)

C

Block diagram and electrical specifications

C (MODE 3: CPOL=1,CPHA=1)

D

Q

MSB

6

5

4

3

2

1

0

Figure 5. Output timing

S

tCH

C

tCLQX

tCL

tSHQZ

tQVCL

Q

MSB OUT MSB-1 OUT

LSB OUT

tQLQH

tQHQL

D

ADDR.LSB IN

(CPOL=0, CPHA=0)

AI01070B

Figure 6. Serial input timing

S

tSLCH

C

tDVCH

tCHDX

tCLCH

D

MSB IN

HIGH IMPEDANCE

tDLDH

tDHDL

Q

(CPOL=0, CPHA=0)

tSHSL

tCLSH

tCHCL

LSB IN

AI01071

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