74F1763 Просмотр технического описания (PDF) - Philips Electronics
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74F1763 Datasheet PDF : 16 Pages
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Philips Semiconductors
Intelligent DRAM controller (IDC)
Product specification
74F1763
FEATURES
• DRAM signal timing generator
• Automatic refresh circuitry
• Selectable row address hold and RAS precharge times
• Facilitates page mode accesses
• Controls 1 MBit DRAMs
• Intelligent burst-mode refresh after page-mode access cycles
PRODUCT DESCRIPTION
The Philips Semiconductors Intelligent Dynamic RAM Controller is a
1 MBit, single-port version of the 74F1764 Dual Port Dynamic RAM
Controller. It contains automatic signal timing, address multiplexing
and refresh control required for interfacing with dynamic RAMs.
Additional features have been added to this device to take
advantage of technological advances in Dynamic RAMs. A
Page-Mode access pin allows the user to assert RAS for the entire
access cycle rather than the pre-defined four-clock-cycle pulse width
used for normal random access cycles. In addition, the user has the
ability to select the RAS precharge time and Row-Address Hold time
to fit the particular DRAMs being used. DTACK has been modified
from previous family parts to become a negative true, tri-stated
output. The options for latched or unlatched address are contained
on a single device by the addition of an Address Latch Enable (ALE)
input. Finally, a burst refresh monitor has been added to ensure
complete refreshing after length page-mode access cycles. With a
maximum clock frequency of 100 MHz, the F1763 is capable of
controlling DRAM arrays with access times down to 40 nsec.
TYPE
74F1763
fMAX
100 MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
150 mA
ORDERING INFORMATION
PACKAGES
COMMERCIAL RANGE
VCC = 5V "10%;
TA = 0_C TO 70_C
48-pin Plastic DIP
N74F1763N
PKG DWG #
SOT240-1
INPUT AND OUTPUT LOADING FAN-OUT TABLENO TAG
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
REQ
DRAM Request Input
1.0/1.0
CP
Clock Input
1.0/1.0
PAGE
Page Mode Select Input
1.0/1.0
PRECHRG RAS Precharge Select Input
1.0/1.0
HLDROW Row Hold Select Input
1.0/1.0
DTACK
Data Transfer Ack. Output
50/80
GNT
Access Grant Output
50/80
RCP
Refresh Clock Input
1.0/1.0
RA0–9
Row Address Inputs
1.0/1.0
CA0–9
Column Address Inputs
1.0/1.0
ALE
Address Latch Enable Input
1.0/1.0
RAS
Row Address Strobe Output
NA
CAS
Column Address Strobe Output
NA
MA0–9
DRAM Address Outputs
NA
NOTES:
One (1.0) FAST Unit Load is defined as 20 mA in the HIGH state and 0.6 mA in the LOW state.
FAST Unit Loads do not correspond to DRAM Input Loads. See Functional Description for details.
LOAD VALUE HIGH/LOW
20 mA/0.6 mA
20 mA/0.6 mA
20 mA/0.6 mA
20 mA/0.6 mA
20 mA/0.6 mA
35 mA/60 mA
35 mA/60 mA
20 mA/0.6 mA
20 mA/0.6 mA
20 mA/0.6 mA
20 mA/0.6 mA
35 mA/60 mA
35 mA/60 mA
35 mA/60 mA
1999 Jan 08
2
853–1406 20619
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