TDA8753 Просмотр технического описания (PDF) - Philips Electronics

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TDA8753

YUV 8-bit analog-to-digital interface

Philips Electronics 

Philips Semiconductors

YUV 8-bit analog-to-digital interface

Product specification

TDA8753A

The TDA8753A registers have address F0, F1 and F2

hexadecimal notation. Whenever the received address

(decoded on the first 8 bits received) is one of these, the

event is recorded in such a way that the next data received

by the TDA8753A will be captured in the line

buffer BF0, BF1 and BF2 respectively.

When 8 bits have been received, the data reception state

is entered. The address reception state can also be exited

at any time when V50 goes HIGH. The F0, F1 and F2

registers may not be loaded properly if there is some

activity in progress on the incoming line.

DATA RECEPTION STATE

The next 8 bits are considered as data bits according to

the format of Fig.4.

When 8 data bits have been received, the data is recorded

in the BF0, BF1 or BF2 line buffers if the previous address

recorded was F0 hex, F1 hex or F2 hex respectively.

The bit count is then reset to zero and the address

reception state is entered. This state may be ended any

time when V50 goes HIGH but in that condition F0, F1 and

F2 registers may not be loaded properly.

handbook, halfpage

incoming stream

last address

bit received

1 1 0 XXXXX

first bit of next

address stream

first data bit of value

(e.g. for address F2 register)

Data value is F2 0:2 = 110(DEL 0:2 )

MBE427

Fig.4 Data reception.

Table 1 Data allocation

ADDRESS

F0H

PARAMETER

CF

F1H

UV_CORING

UV_FILTER_TYPE

PRE_ON

NOTCH_ON

DTO_ON

SEL_DTO_RES

WEO_DEL_SEL

F2H

Y_VAR_DELAY

FUNCTION

compression factor value will be (1 + cf/255)

which results in a range from 1 to 2

coring definition in U and V channels; see Table 5

notch filter selection in U and V channels

(0 = 4 MHz; 1 = 2 MHz)

luminance prefilter active

notch prefilter active

DTO control

select DTO reset (0 = WE; 1 = Href)

select delay in WEO

luminance delay compression (see Table 5)

not used; load 0

NUMBER

OF BITS

8

2

1

1

1

1

1

5

BIT

POSITION

7:0

1:0

2

3

4

5

6

7:2

1996 Jan 12

6

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