ISL6252 Просмотр технического описания (PDF) - Intersil

Номер в каталоге

Компоненты Описание

производитель

ISL6252

Highly Integrated Battery Charger Controller for Notebook Computers

Intersil 

ISL6252, ISL6252A

The output capacitor creates a pole at a very high frequency

due to the small resistance in parallel with it. The frequency

of this pole is calculated in Equation 30:

fPOLE2

=

------------------1--------------------

2π ⋅ Co ⋅ RBAT

(EQ. 30)

CHARGE CURRENT CONTROL LOOP

When the battery voltage is less than the fully charged

voltage, the voltage error amplifier goes to it’s maximum

output (limited to 1.2V above ICOMP) and the ICOMP

voltage controls the loop through the minimum voltage

buffer. Figure 19 shows the charge current control loop.

PHASE

L

11

R FET_rDS(ON)

R L_DCR

+

SΣ

0.25

-

ICOMP

CICOMP

-

gm2

+

+

20

-

CA2

CSOP

CSON

CHLIM

+

-

R F2

C F2

R S2

CO

RESR

R BAT

FIGURE 19. CHARGE CURRENT LIMIT LOOP

The compensation capacitor (CICOMP) gives the error

amplifier (GMI) a pole at a very low frequency (<<1Hz) and a

a zero at fZ1. fZ1 is created by the 0.25*CA2 output added to

ICOMP. The frequency of can be calculated from

Equation 31:

fZERO

=

----------4-----⋅---g----m-----2------------

(2π ⋅ CICOMP)

gm2

=

5----0----μ----A--

V

(EQ. 31)

Placing this zero at a frequency equal to the pole calculated

in Equation 29 will result in maximum gain at low frequencies

and phase margin near 90°. If the zero is at a higher

frequency (smaller CICOMP), the DC gain will be higher but

the phase margin will be lower. Use a capacitor on ICOMP

that is equal to or greater than the value calculated in

Equation 32:

CICOMP

=

----------------------------4-----⋅---(--5----0---μ----A------⁄--V-----)---------------------------

(RS2 + rDS(ON) + RDCR + RBAT)

(EQ. 32)

A filter should be added between RS2 and CSOP and CSON

to reduce switching noise. The filter roll off frequency should

be between the cross over frequency and the switching

frequency (~100kHz). RF2 should be small (<10Ω) to

minimize offsets due to leakage current into CSOP. The filter

cut off frequency is calculated using Equation 33:

fFILTER = (---2----π-----⋅---C----F-1---2----⋅---R-----F---2----)

(EQ. 33)

The cross over frequency is determined by the DC gain of

the modulator and output filter and the pole in Equation 23.

The DC gain is calculated in Equation 34 and the cross over

frequency is calculated with Equation 35.

ADC = (---R-----S---2-----+-----r--D----S----(--O-----N----)1---+-1----R-⋅---R-D---S-C---2-R-----+-----R-----B----A---T----T----E----R----Y----)

(EQ. 34)

fCO

=

ADC ⋅ fPOLE

=

-1---1-----⋅---R----S----2-

2π ⋅ L

(EQ. 35)

The bode plot of the loop gain, the compensator gain and

the power stage gain is shown in Figure 20:

60

COMPENSATOR

fZERO

MODULATOR

40

LOOP

20

0

-20

fPOLE1

fFILTER

-40

-60

0.01k

fPOLE2

0.1k

1k

10k

FREQUENCY (Hz)

100k

1M

FIGURE 20. CHARGE CURRENT LOOP BODE PLOTS

Adapter Current Limit Control Loop

If the combined battery charge current and system load

current draws current that equals the adapter current limit

set by the ACLIM pin, ISL6252 will reduce the current to the

battery and/or reduce the output voltage to hold the adapter

current at the limit. Above the adapter current limit, the

minimum current buffer equals the output of gm3 and

ICOMP controls the charger output. Figure 21 shows the

adapter current limit control loop.

DCIN

RS1

RF1

PHASE

L

11

R FET_rDS(ON)

RL_DCR

CF1

Σ

CSIN

CSIP

ICOMP

CICOMP

+

0.25

-

- 20

+

CA1

+

20

-

CA2

CSOP

CSON

-

gm3

+

ACLIM +

-

RF2

C F2

R

CO

RESR

FIGURE 21. ADAPTER CURRENT LIMIT LOOP

19

FN6498.1

July 19, 2007

Share Link: