ISL6252 Просмотр технического описания (PDF) - Intersil

Номер в каталоге

Компоненты Описание

производитель

ISL6252

Highly Integrated Battery Charger Controller for Notebook Computers

Intersil 

ISL6252, ISL6252A

The inductor ripple current ΔI is found from Equation 17:

IRIPPLE = 0.3 ⋅ IL, MAX

(EQ. 17)

where the maximum peak-to-peak ripple current is 30% of

the maximum charge current is used.

For VIN,MAX = 19V, VBAT = 16.8V, IBAT,MAX = 2.6A, and

fs = 300kHz, the calculated inductance is 8.3µH. Choosing

the closest standard value gives L = 10µH. Ferrite cores are

often the best choice since they are optimized at 300kHz to

600kHz operation with low core loss. The core must be large

enough not to saturate at the peak inductor current IPeak in

Equation 18:

IPEAK

=

IL,

M

A

X

+

1--

2

⋅

IR

IPP

L

E

(EQ. 18)

Inductor saturation can lead to cascade failures due to very

high currents. Conservative design limits the peak and RMS

current in the inductor to less than 90% of the rated

saturation current.

Cross over frequency is heavily dependant on the inductor

value. fCO should be less than 20% of the switching

frequency and a conservative design has fCO less than 10%

of the switching frequency. The highest fCO is in voltage

control mode with the battery removed and may be

calculated (approximately) from Equation 19:

fCO = 5-----⋅---1----1---2--⋅-π-R----⋅-S--L--E----N----S----E--

(EQ. 19)

Output Capacitor Selection

The output capacitor in parallel with the battery is used to

absorb the high frequency switching ripple current and

smooth the output voltage. The RMS value of the output

ripple current Irms is given by Equation 20:

IRMS

=

------V----I--N----,---M----A----X-------- ⋅ D ⋅ (1 – D)

12 ⋅ L ⋅ FSW

(EQ. 20)

where the duty cycle D is the ratio of the output voltage

(battery voltage) over the input voltage for continuous

conduction mode which is typical operation for the battery

charger. During the battery charge period, the output voltage

varies from its initial battery voltage to the rated battery

voltage. So, the duty cycle change can be in the range of

between 0.53 and 0.88 for the minimum battery voltage of

10V (2.5V/Cell) and the maximum battery voltage of 16.8V.

The maximum RMS value of the output ripple current occurs

at the duty cycle of 0.5 and is expressed as Equation 21:

IRMS

=

---------V----I--N----,---M----A----X-----------

4 ⋅ 12 ⋅ L ⋅ fSW

(EQ. 21)

For VIN,MAX = 19V, VBAT = 16.8V, L = 10µH, and

fs = 300kHz, the maximum RMS current is 0.19A. A typical

10F ceramic capacitor is a good choice to absorb this

current and also has very small size. Organic polymer

capacitors have high capacitance with small size and have a

significant equivalent series resistance (ESR). Although

ESR adds to ripple voltage, it also creates a high frequency

zero that helps the closed loop operation of the buck

regulator.

EMI considerations usually make it desirable to minimize

ripple current in the battery leads. Beads may be added in

series with the battery pack to increase the battery

impedance at 300kHz switching frequency. Switching ripple

current splits between the battery and the output capacitor

depending on the ESR of the output capacitor and battery

impedance. If the ESR of the output capacitor is 10mΩ and

battery impedance is raised to 2Ω with a bead, then only

0.5% of the ripple current will flow in the battery.

MOSFET Selection

The Notebook battery charger synchronous buck converter

has the input voltage from the AC adapter output. The

maximum AC adapter output voltage does not exceed 25V.

Therefore, 30V logic MOSFET should be used.

The high side MOSFET must be able to dissipate the

conduction losses plus the switching losses. For the battery

charger application, the input voltage of the synchronous

buck converter is equal to the AC adapter output voltage,

which is relatively constant. The maximum efficiency is

achieved by selecting a high side MOSFET that has the

conduction losses equal to the switching losses. Switching

losses in the low-side FET are very small. The choice of

low-side FET is a trade off between conduction losses

(rDS(ON)) and cost. A good rule of thumb for the rDS(ON) of

the low-side FET is 2X the rDS(ON) of the high-side FET.

The LGATE gate driver can drive sufficient gate current to

switch most MOSFETs efficiently. However, some FETs may

exhibit cross conduction (or shoot through) due to current

injected into the drain-to-source parasitic capacitor (Cgd) by

the high dV/dt rising edge at the phase node when the high-

side MOSFET turns on. Although LGATE sink current (1.8A

typical) is more than enough to switch the FET off quickly,

voltage drops across parasitic impedances between LGATE

and the MOSFET can allow the gate to rise during the fast

rising edge of voltage on the drain. MOSFETs with low

threshold voltage (<1.5V) and low ratio of Cgs/Cgd (<5) and

high gate resistance (>4Ω) may be turned on for a few ns by

the high dV/dt (rising edge) on their drain. This can be

avoided with higher threshold voltage and Cgs/Cgd ratio.

Another way to avoid cross conduction is slowing the turn-on

speed of the high-side MOSFET by connecting a resistor

between the BOOT pin and the boot strap cap.

For the high-side MOSFET, the worst-case conduction

losses occur at the minimum input voltage as shown in

Equation 22:

PQ1, conduction

=

V-----O----U----T--

VIN

⋅

IB

A

2

T

⋅

rDS(ON)

(EQ. 22)

The optimum efficiency occurs when the switching losses

equal the conduction losses. However, it is difficult to

16

FN6498.1

July 19, 2007

Share Link: