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IS93C66-3

4096-BIT SERIAL ELECTRICALLY ERASABLE PROM

Integrated Silicon Solution 

IS93C66-3

ISSI ®

remains in a write disabled state until a WEN instruction

is executed. Thereafter, the device remains enabled until

a WDS instruction is executed or until Vcc is removed.

(NOTE: Neither the WEN nor the WDS instruction has any

effect on the READ instruction.) (See Figure 4.)

Write (WRITE)

The WRITE instruction includes 16 bits of data to be

written into the specified register. After the last data bit

has been applied to DIN, and before the next rising edge of

SK, CS must be brought LOW. The falling edge of CS

initiates the self-timed programming cycle.

After a minimum wait of 250 ns (5V operation) from the

falling edge of CS (tCS), if CS is brought HIGH, DOUT will

indicate the READY/BUSY status of the chip: logical “0”

means programming is still in progress; logical “1” means

the selected register has been written, and the part is

ready for another instruction (see Figure 5). (NOTE: The

combination of CS HIGH, DIN HIGH and the rising edge of

the SK clock, resets the READY/BUSY flag. Therefore, it

is important if you want to access the READY/BUSY flag

not to reset it through this combination of control signals.)

Before a WRITE instruction can be executed, the device

must be write enabled (see WEN).

Write All (WRALL)

The write all (WRALL) instruction programs all registers

with the data pattern specified in the instruction. While the

WRALL instruction is being loaded, the address field

becomes a sequence of “Don’t Care” bits (see Figure 6).

As with the WRITE instruction, if CS is brought HIGH after

a minimum wait of 250 ns (tCS), the DOUT pin indicates the

READY/BUSY status of the chip (see Figure 6).

Write Disable (WDS)

The write disable (WDS) instruction disables all

programming capabilities. This protects the entire part

against accidental modification of data until a WEN

instruction is executed. (When Vcc is applied, this part

powers up in the write disabled state.) To protect data, a

WDS instruction should be executed upon completion of

each programming operation. (NOTE: Neither the WEN

nor the WDS instruction has any effect on the READ

instruction.) (See Figure 7.)

Erase Register (ERASE)

After the erase instruction is entered, CS must be brought

LOW. The falling edge of CS initiates the self-timed

internal programming cycle. Bringing CS HIGH after a

minimum of tCS, will cause DOUT to indicate the READ/BUSY

status of the chip: a logical “0” indicates programming is

still in progress; a logical “1” indicates the erase cycle is

complete and the part is ready for another instruction (see

Figure 8).

Erase All (ERAL)

Full chip erase is provided for ease of programming.

Erasing the entire chip involves setting all bits in the entire

memory array to a logical “1” (see Figure 9).

INSTRUCTION SET

Instruction

Start Bit

OP Code

Address

Input Data

READ

1

10

(A7-A0)

WEN

(Write Enable)

1

00

11XXXXXX

WRITE

1

01

(A7-A0)

D15-D0(1)

WRALL

1

(Write All Registers)

00

01XXXXXX

D15-D0(1)

WDS

(Write Disable)

1

00

00XXXXXX

ERASE

1

11

(A7-A0)

ERAL

1

(Erase All Registers)

00

10XXXXXX

Note: 1. If input data is not 16 bits exactly, the last 16 bits will be taken as input data (a word).

Integrated Silicon Solution, Inc. — 1-800-379-4774

3

Rev. G

04/26/01

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