DS1992L-F5 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS1992L-F5

1kb/4kb Memory iButton

Dallas Semiconductor -> Maxim Integrated 

DS1992/DS1993

Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSE

VPULLUP

VPULLUP MIN

VIH MIN

MASTER TX

"RESET PULSE"

MASTER RX "PRESENCE PULSE"

tRSTH

VIL MAX

0V

RESISTOR

MASTER

DS199X

tRSTL

tR

tPDH

480 µs £ tRSTL < ¥*

480 µs £ tRSTH < ¥**

15 µs £ tPDH < 60 µs

60 £ tPDL < 240 µs

tPDL

* In order not to mask interrup signaling

by other devices on the 10Wire bus tRSTL

+ tR should always be less than 960 us

** Includes recovery time

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 11. The master driving the data line

low initiates all time slots. The falling edge of the data line synchronizes the DS199_ to the master by

triggering a delay circuit in the DS199_. During write time slots, the delay circuit determines when the

DS199_ samples the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit

determines how long the DS199_ holds the data line low overriding the 1 generated by the master. If the

data bit is a 1, the iButton leaves the read data time slot unchanged.

Figure 11. READ/WRITE TIMING DIAGRAM

Write-One Time Slot

VPULLUP

VPULLUP MIN

VIH MIN

VIL MAX

0V

RESISTOR

MASTER

tSLOT

DS199X

Sampling Window

tLOW1

15µs

60µs

60 µs £ tSLOT < 120 µs

1 µs £ tLOW1 < 15 µs

1 µs £ tREC < ¥

tREC

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