IP101A Просмотр технического описания (PDF) - Unspecified

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IP101A

Single port 10/100 Fast Ethernet Transceiver

Unspecified 

7.2 A.C. Characteristic

7.2.1 MII Timing

a. Pin Reset and Clock output timing relationship

Symbol

Tdelay

Description

Delay time after reset to clock output

Tdelay

RESET_N

MII_TXCLK

MII_RXCLK

IP101A LF

Data Sheet

Min. Typ. Max. Unit

-

40

-

us

b. Transmit Timing Requirements

Symbol

TTxClk

TTxClk

TsTxClk

ThTxClk

Description

Transmit clock period 100M MII

Transmit clock period 10M MII

TXEN, TXD to MII_TXCLK setup time

TXEN, TXD to MII_TXCLK hold time

T TxClk

M II_ T X C L K

TXEN, TXD[3:0]

T sTxClk

T hTxClk

Min. Typ. Max. Unit

-

40

-

ns

-

400

-

ns

2

-

-

ns

0.5

-

-

ns

c. Receive Timing

Symbol

TRxClk

TRxClk

TdRxClk

Description

Receive clock period 100M MII

Receive clock period 10M MII

MII_RXCLK falling edge to RXDV, RXD

TRxClk

MII_RXCLK

RXDV, RXD[3:0]

Copyright © 2004, IC Plus Corp.

T dRxClk

32/36

Min. Typ. Max. Unit

-

40

-

ns

-

400

-

ns

1

-

4

ns

Oct 22, 2007

IP101A LF-DS-R12

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