IDT72V3672 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V3672 Datasheet PDF : 29 Pages
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IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
if a word in memory is the next data to be sent to the FlFO output register and
two cycles of the port Clock that reads data from the FIFO have not elapsed
since the time the word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing clock occurs,
forcing the Empty Flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
clock begins the first synchronization cycle of a write if the clock transition occurs
at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 8 through 11 for EFA/ORA
and EFB/ORB timing diagrams).
FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)
This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and IRB)
function is selected. In IDT Standard mode, the Full Flag (FFA and FFB)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array. For both FWFT and IDT Standard modes, each time
a word is written to a FIFO, its write pointer is incremented. The state machine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, a Full/Input Ready flag is LOW if less than two
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
next memory write location has been read. The second LOW-to-HIGH
transition on the Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can
be the first synchronization cycle (see Figures 12 through 15 for FFA/IRA and
FFB/IRB timing diagrams).
ALMOST-EMPTY FLAGS ( AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
data from its array. The state machine that controls an Almost-Empty flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-empty state is defined by the contents of register X1 for AEB and register
X2 for AEA. These registers are loaded with preset values during a FIFO reset
or programmed from port A (see Almost-Empty flag and Almost-Full flag offset
programming section). An Almost-Empty flag is LOW when its FIFO contains
X or less words and is HIGH when its FIFO contains (X+1) or more words. A
data word present in the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing
clock are required after a FIFO write for its Almost-Empty flag to reflect the new
level of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more
words remains LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An Almost-Empty flag
is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after
the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of
an Almost-Empty flag synchronizing clock begins the first synchronization cycle
if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be the first synchro-
nization cycle. (See Figures 16 and 17).
ALMOST-FULL FLAGS (AFA, AFB)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors a
write pointer and read pointer comparator that indicates when the FIFO memory
status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined
by the contents of register Y1 for AFA and register Y2 for AFB. These registers
are loaded with preset values during a FlFO reset or programmed from port
A (see Almost-Empty flag and Almost-Full flag offset programming section).
An Almost-Full flag is LOW when the number of words in its FIFO is greater than
or equal to (2,048-Y), (4,096-Y), or (8,192-Y) for the IDT72V3652, IDT72V3662,
or IDT72V3672 respectively. An Almost-Full flag is HIGH when the number
of words in its FIFO is less than or equal to [2,048-(Y+1)], [4,096-(Y+1)], or
[8,192-(Y+1)] for the IDT72V3652, IDT72V3662, or IDT72V3672 respec-
tively. Note that a data word present in the FIFO output register has been read
from memory.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock
are required after a FIFO read for its Almost-Full flag to reflect the new level of
fill. Therefore, the Almost-Full flag of a FIFO containing [2,048/4,096/8,192-
(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have
not elapsed since the read that reduced the number of words in memory to
[2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-
to-HIGH transition of its synchronizing clock after the FIFO read that reduces
the number of words in memory to [2,048/4,096/8,192-(Y+1)]. A LOW-to-HIGH
transition of an Almost-Full flag synchronizing clock begins the first synchroni-
zation cycle if it occurs at time tSKEW2 or greater after the read that reduces the
number of words in memory to [2,048/4,096/8,192-(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figures 18 and 19).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between port A and port B without putting it in queue. The Mailbox
select (MBA, MBB) inputs choose between a mail register and a FIFO for a port
data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data
to the mail1 register when a port A Write is selected by CSA, W/RA, and ENA
and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data
to the mail2 register when a port B Write is selected by CSB, W/RB, and ENB
and with MBB HIGH. Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while
the mail flag is LOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the mail
register when the port mailbox select input is HIGH. The Mail1 Register Flag
(MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port B Read
is selected by CSB, W/RB, and ENB and with MBB HIGH. The Mail2 Register
Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port
A read is selected by CSA, W/RA, and ENA and with MBA HIGH. The data
in a mail register remains intact after it is read and changes only when new data
is written to the register. For mail register and Mail Register Flag timing diagrams,
see Figure 20 and 21.
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