9LPRS502YKLFT Просмотр технического описания (PDF) - Integrated Device Technology
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9LPRS502YKLFT
Integrated Device Technology
9LPRS502YKLFT Datasheet PDF : 29 Pages
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ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
SSOP/TSSOP Pin Description (Continued)
PIN #
PIN NAME
48 CK_PWRGD/PD#
49 FSLB/TEST_MODE
50 GNDREF
51 X2
52 X1
53 VDDREF
54 REF0/FSLC/TEST_SEL
55 SDATA
56 SCLK
TYPE
IN
IN
PWR
OUT
IN
PWR
I/O
I/O
IN
DESCRIPTION
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS
and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider
mode while in test mode. Refer to Test Clarification Table.
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched
input to enable test mode. Refer to Test Clarification Table.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Fully Integrated Regulator Connection for Desktop/Mobile Applications
ICS9LPR502
ICS9LPRS502
VDDCPU_IO, Pin 41
NC
PIN 40
1.05V to 3.3V
(+/-5%)
CPU_IO Decoupling
Network
96_IO Decoupling
Network
PLL3_IO Decoupling
Network
SRC_IO Decoupling
Network
VDDSRC_IO Pin 37, 26
VDDPLL3_IO, Pin 20
VDD96_IO, Pin 12
IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
5
1125E—02/26/09
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