ICS94225 Просмотр технического описания (PDF) - Integrated Circuit Systems

Номер в каталоге

Компоненты Описание

производитель

ICS94225

AMD-K7™ System Clock Chip

Integrated Circuit Systems 

ICS94225

CPU_STOP# Timing Diagram

CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power

operation. CPU_STOP# is synchronized by the ICS94225. All other clocks will continue to run while the CPUCLKs

clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees

the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than

4 CPUCLKs.

INTERNAL

CPUCLK

PCICLK

CPU_STOP#

PD# (High)

CPUCLKT

CPUCLKC

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is

synchronized to the CPUCLKs inside the ICS94225.

3. All other clocks continue to run undisturbed.

4. PD# and PCI_STOP# are shown in a high (true) state.

0445B—08/01/03

15

Share Link: