HT56R65 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT56R65

TinyPower™ A/D Type with LCD 8-Bit OTP MCU

Holtek Semiconductor 

HT56R62/HT56R65

HT56R642/HT56R644/HT56R654/HT56R656

TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

System Architecture

A key factor in the high-performance features of the Holtek range of microcontrollers is attributed

to their internal system architecture. The range of devices take advantage of the usual features found

within RISC microcontrollers providing increased speed of operation and enhanced performance.

The pipelining scheme is implemented in such a way that instruction fetching and instruction

execution are overlapped, hence instructions are effectively executed in one cycle, with the

exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set

operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement,

branch decisions, etc. The internal data path is simplified by moving data through the Accumulator

and the ALU. Certain internal registers are implemented in the Data Memory and can be directly

or indirectly addressed. The simple addressing methods of these registers along with additional

architectural features ensure that a minimum of external components is required to provide a

functional I/O and A/D control system with maximum reliability and flexibility. This makes the

device suitable for low-cost, high-volume production for controller applications.

Clocking and Pipelining

The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into

four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at

the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4

clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms

one instruction cycle. Although the fetching and execution of instructions takes place in consecutive

instruction cycles, the pipelining structure of the microcontroller ensures that instructions are

effectively executed in one instruction cycle. The exception to this are instructions where the

contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the

instruction will take one more instruction cycle to execute.

When the RC oscillator is used, OSC2 is free for use as a T1 phase clock synchronizing pin. This T1

phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle.

O s c illa to r C lo c k

( S y s te m C lo c k )

P h a s e C lo c k T 1

P h a s e C lo c k T 2

P h a s e C lo c k T 3

P h a s e C lo c k T 4

P ro g ra m C o u n te r

PC

PC +1

PC +2

P ip e lin in g

F e tc h In s t. (P C )

E x e c u te In s t. (P C -1 )

F e tc h In s t. (P C + 1 )

E x e c u te In s t. (P C )

System Clocking and Pipelining

F e tc h In s t. (P C + 2 )

E x e c u te In s t. (P C + 1 )

Rev. 1.30

21

March 6, 2013

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