HT49CA0 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT49CA0

Remote Type 8-Bit MCU with LCD

Holtek Semiconductor 

HT49RA0/HT49CA0

The internal Timer/Event Counter interrupt is initialized

by setting the Timer/Event Counter interrupt request flag

(TF;bit 6 of INTC0), which is normally caused by a timer

overflow. After the interrupt is enabled, and the stack is

not full, and the TF bit is set, a subroutine call to location

0CH occurs. The related interrupt request flag (TF) is re-

set, and the EMI bit is cleared to disable further interrupts.

The time base interrupt is initialized by setting the time

base interrupt request flag (TBF;bit 4 of INTC1), that is

caused by a regular time base signal. After the interrupt

is enabled, and the stack is not full, and the TBF bit is

set, a subroutine call to location 10H occurs. The related

interrupt request flag (TBF) is reset and the EMI bit is

cleared to disable further interrupts.

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF; bit 5 of

INTC1), that is caused by a regular real time clock signal.

After the interrupt is enabled, and the stack is not full, and

the RTF bit is set, a subroutine call to location 14H oc-

curs. The related interrupt request flag (RTF) is reset and

the EMI bit is cleared to disable further interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are all held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set both to 1 (if the stack is not

full). To return from the interrupt subroutine, ²RET² or

²RETI² may be invoked. RETI sets the EMI bit and en-

ables an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

priorities in the following table apply. These can be

masked by resetting the EMI bit.

Interrupt Source

External interrupt 0

External interrupt 1

Timer/Event Counter overflow

Time base interrupt

Real time clock interrupt

Priority

1

2

3

4

5

Vector

04H

08H

0CH

10H

14H

The EMI, EEI0, EEI1, ETI, ETBI and ERTI are all used to

control the enable/disable status of interrupts. These

bits prevent the requested interrupt from being serviced.

Once the interrupt request flags (RTF, TBF, TF, EIF1,

EIF0) are all set, they remain in the INTC1 or INTC0 re-

spectively until the interrupts are serviced or cleared by

a software instruction.

Bit No.

0

1

2

3

4

5

6

7

Bit No.

0

1

2, 3

4

5

6, 7

Rev. 1.20

Label

EMI

EEI0

EEI1

ETI

EIF0

EIF1

TF

¾

Label

ETBI

ERTI

¾

TBF

RTF

¾

Function

Controls the master (global) interrupt (1=enabled; 0=disabled)

Controls the external interrupt 0 (1=enabled; 0=disabled)

Controls the external interrupt 1 (1=enabled; 0=disabled)

Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)

External interrupt 0 request flag (1=active; 0=inactive)

External interrupt 1 request flag (1=active; 0=inactive)

Internal Timer/Event Counter request flag (1=active; 0=inactive)

Unused bit, read as ²0²

INTC0 (0BH) Register

Function

Controls the time base interrupt (1=enabled; 0:disabled)

Controls the real time clock interrupt (1=enabled; 0:disabled)

Unused bit, read as ²0²

Time base request flag (1=active; 0=inactive)

Real time clock request flag (1=active; 0=inactive)

Unused bit, read as ²0²

INTC1 (1EH) Register

9

October 24, 2007

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