HT46C62 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT46C62

A/D with LCD Type 8-Bit MCU

Holtek Semiconductor 

HT46R62/HT46C62

flows, the counter is reloaded from the timer/event coun-

ter register and issues an interrupt request, as in the

other two modes, i.e., event and timer modes.

To enable the counting operation, the Timer ON bit

(TON; bit 4 of TMRC) should be set to 1. In the pulse

width measurement mode, the TON is automatically

cleared after the measurement cycle is completed. But

in the other two modes, the TON can only be reset by in-

structions. The overflow of the Timer/Event Counter is

one of the wake-up sources and can also be applied to a

PFD (Programmable Frequency Divider) output at PA3

by options. Only one PFD can be applied to PA3 by op-

tions . No matter what the operation mode is, writing a 0

to ETI disables the related interrupt service. When the

PFD function is selected, executing ²SET [PA].3² in-

struction to enable PFD output and executing ²CLR

[PA].3² instruction to disable PFD output.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turn on, data written to the

timer/event counter is kept only in the timer/event coun-

ter preload register. The timer/event counter still contin-

ues its operation until an overflow occurs.

When the timer/event counter (reading TMR) is read,

the clock is blocked to avoid errors, as this may results

Bit No.

0

1

2

3

4

5

6

7

Label

PSC0

PSC1

PSC2

TE

TON

¾

TM0

TM1

Function

To define the prescaler stages.

PSC2, PSC1, PSC0=

000: fINT=fSYS

001: fINT=fSYS/2

010: fINT=fSYS/4

011: fINT=fSYS/8

100: fINT=fSYS/16

101: fINT=fSYS/32

110: fINT=fSYS/64

111: fINT=fSYS/128

Defines the TMR active edge of the timer/event counter:

In Event Counter Mode (TM1,TM0)=(0,1):

1:count on falling edge;

0:count on rising edge

In Pulse Width measurement mode (TM1,TM0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

Enable/disable timer counting (0=disabled; 1=enabled)

Unused bit, read as ²0²

Defines the operating mode (TM1, TM0)

01= Event count mode (External clock)

10= Timer mode (Internal clock)

11= Pulse Width measurement mode (External clock)

00= Unused

TMRC (0EH) Register

PW M

(6 + 2 ) o r (7 + 1 )

C o m p a re

T o P D 0 /P D 1 /P D 2 C ir c u it

fS Y S

8 - s ta g e P r e s c a le r

fIN T

8 -1 M U X

TM 1

TM 0

P S C 2~P S C 0 TM R

TE

D a ta B u s

8 - b it T im e r /E v e n t C o u n te r R e lo a d

P r e lo a d R e g is te r

TM 1

TM 0

P u ls e W id th

M e a s u re m e n t

M o d e C o n tro l

TO N

8 - b it T im e r /E v e n t C o u n te r

(T M R )

O v e r flo w to In te r r u p t

1 /2

PFD

Timer/Event Counter

P A 3 D a ta C T R L

Rev. 1.60

17

July 14, 2005

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