HT46R52A Просмотр технического описания (PDF) - Holtek Semiconductor

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HT46R52A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R51A/HT46R52A

The definitions of the PFD control signal and PFD output

frequency are listed in the following table.

Timer

Timer

Preload

Value

PA3 Data

Register

PA3 Pad

State

Frequency

OFF X

0

0

X

OFF X

1

U

X

ON

N

0

0

X

ON

N

1

PFD fINT/(2´(256-N))

Note:

²X² stands for ²unused²

²U² stands for ²unknown²

²N² is the preload value for the timer/event

counter

²fTMR² is the input clock frequency for the

timer/event counter

The PB can also be used as A/D converter inputs. The

A/D function will be described later. There is a PWM

function shared with PD0. If the PWM function is en-

abled, the PWM signal will appear on PD0 (if PD0 is op-

erating in output mode). The I/O functions of PD0 are as

shown.

I/O

Mode

PD0

I/P

O/P

(Normal) (Normal)

Logical Logical

Input Output

I/P

(PWM)

Logical

Input

O/P

(PWM)

PWM

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

PWM

The microcontroller provides one channel PWM output

shared with PD0. The PWM supports 6+2 mode. The

PWM channel has their data register denoted as

PWM(1AH). The frequency source of the PWM counter

comes from fSYS. The PWM register is an 8-bit register.

The waveforms of the PWM outputs are as shown.

Once the PD0 are selected as the PWM outputs and the

output function of the PD0 are enabled (PDC.0= ²0²),

writing ²1² to PD0 data register will enable the PWM out-

put function and writing ²0² will force the PD0 to stay at

²0².

A (6+2) bits mode PWM cycle is divided into four modu-

lation cycles (modulation cycle 0~modulation cycle 3).

Each modulation cycle has 64 PWM input clock period.

In a (6+2) bit PWM function, the contents of the PWM

register is divided into two groups. Group 1 of the PWM

register is denoted by DC which is the value of

PWM.7~PWM.2. The group 2 is denoted by AC which is

the value of PWM.1~PWM.0. In a (6+2) bits mode PWM

cycle, the duty cycle of each modulation cycle is shown

in the table.

Parameter

Modulation cycle i

(i=0~3)

AC (0~3) Duty Cycle

i<AC

DC+ 1

64

DC

i³AC

64

The modulation frequency, cycle frequency and cycle

duty of the PWM output signal are summarized in the

following table.

PWM

PWM Cycle PWM Cycle

Modulation Frequency Frequency Duty

fSYS/64 for (6+2) bits mode fSYS/256 [PWM]/256

fS Y S /2

[P W M ] = 1 0 0

PW M

2 5 /6 4

2 5 /6 4

2 5 /6 4

[P W M ] = 1 0 1

PW M

2 6 /6 4

2 5 /6 4

2 5 /6 4

[P W M ] = 1 0 2

PW M

2 6 /6 4

2 6 /6 4

2 5 /6 4

[P W M ] = 1 0 3

PW M

2 6 /6 4

2 6 /6 4

2 6 /6 4

P W M m o d u la tio n p e r io d : 6 4 /fS Y S

M o d u la tio n c y c le 0

M o d u la tio n c y c le 1

M o d u la tio n c y c le 2

P W M c y c le : 2 5 6 /fS Y S

(6+2) PWM Mode

2 5 /6 4

2 5 /6 4

2 5 /6 4

2 5 /6 4

M o d u la tio n c y c le 3

2 5 /6 4

2 6 /6 4

2 6 /6 4

2 6 /6 4

M o d u la tio n c y c le 0

Rev. 1.30

16

March 6, 2009

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