HT46R52A Просмотр технического описания (PDF) - Holtek Semiconductor

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HT46R52A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R51A/HT46R52A

Input/Output Ports

There are 14 bidirectional input/output lines in the

, labeled as PA, PB and PD, which are

mapped to the data memory of [12H], [14H] and [18H]

respectively. All of these I/O ports can be used for input

and output operations. For input operation, these ports

are non-latching, that is, the inputs must be ready at the

T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H

or 18H). For output operation, all the data is latched and

remains unchanged until the output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PDC) to control the input/output configuration. With this

control register, CMOS output or Schmitt trigger input

with or without pull-high resistor structures can be re-

configured dynamically under software control. To func-

tion as an input, the corresponding latch of the control

register must write ²1². The input source also depends

on the control register. If the control register bit is ²1²,

the input will read the pad state. If the control register bit

is ²0², the contents of the latches will move to the inter-

nal bus. The latter is possible in the ²read-modify-write²

instruction.

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H and 19H.

After a chip reset, these input/output lines remain at high

levels or floating state (dependent on pull-high options).

Each bit of these input/output latches can be set or

cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or

18H) instructions.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. Each I/O port has a pull-high option. Once the

pull-high option is selected, the I/O port has a pull-high

resistor, otherwise, there¢s none. Take note that a non-

pull-high I/O port operating in input mode will cause a

floating state.

The PA3, PA4 and PA5 are pin-shared with PFD, TMR

and INT pins respectively.

If the PFD option is selected, the output signal in output

mode of PA3 will be the PFD signal generated by the

timer/event counter overflow signal. The input mode al-

ways remain in its original functions. Once the PFD op-

tion is selected, the PFD output signal is controlled by

the PA3 data register only. The I/O functions of PA3 are

shown below.

I/O

I/P

O/P

I/P

Mode (Normal) (Normal) (PFD)

O/P

(PFD)

PA3

Logical

Input

Logical

Output

Logical

PFD

Input (Timer on)

Note: The PFD frequency is the timer/event counter

overflow frequency divided by 2.

V DD

D a ta B u s

W r ite C o n tr o l R e g is te r

C h ip R e s e t

R e a d C o n tr o l R e g is te r

W r ite D a ta R e g is te r

[P A 3 , P F D ]

o r [P D 0 ,P W M ]

R e a d D a ta R e g is te r

S y s te m W a k e - u p ( P A o n ly )

IN T fo r P A 5

T M R fo r P A 4

C o n tr o l B it P u ll- h ig h

DQ

CK Q

S

D a ta B it

DQ

CK Q

S

M

U

X

M

U

X

E N (P F D o r P W M )

W a k e -u p

P A 0~P A 2

P A 3 /P F D

P A 4 /T M R

P A 5 /IN T

PA6

PA7

P B 0 /A N 0 ~ P B 4 /A N 4

P D 0 /P W M

Input/Output Ports

Rev. 1.30

15

March 6, 2009

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