HT46R52A Просмотр технического описания (PDF) - Holtek Semiconductor
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HT46R52A Datasheet PDF : 43 Pages
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HT46R51A/HT46R52A
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
TO PDF
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state. When a system re-
set occurs, the SST delay is added during the reset pe-
riod. Any wake-up from the HALT will enable the SST
delay. An extra option load time delay is added during
system reset (Power-up, WDT time-out at normal mode
or RES reset).
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
Prescaler, Divider Cleared
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter Off
Input/Output Ports Input mode
Stack Pointer
Points to the top of the stack
VDD
RES
S S T T im e - o u t
tS S T + tO P D
C h ip R e s e t
Reset Timing Chart
V DD
100kW
0 .1 m F
RES
B a s ic
R eset
C ir c u it
V DD
0 .0 1 m F
100kW
10kW
0 .1 m F
RES
H i-n o is e
R eset
C ir c u it
Reset Circuit
Note:
Most applications can use the Basic Reset Cir-
cuit as shown, however for applications with ex-
tensive noise, it is recommended to use the
Hi-noise Reset Circuit.
H A LT
W DT
W DT
T im e - o u t
R eset
RES
E x te rn a l
O SC1
SST
1 0 - b it R ip p le
C o u n te r
W a rm R e s e t
C o ld
R eset
P o w e r - o n D e te c tio n
Reset Configuration
The register states are summarized below:
Register
Reset(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMRC
00-0 1000
00-0 1000
00-0 1000
Program
Counter
0000H
0000H
0000H
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
MP1
xxxx xxxx
xxxx xxxx
xxxx xxxx
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
INTC
-000 0000
-000 0000
-000 0000
RES Reset
(HALT)
xxxx xxxx
00-0 1000
0000H
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
-uuu uuuu
--01 uuuu
-000 0000
WDT Time-out
(HALT)*
uuuu uuuu
uu-u uuuu
0000H
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--11 uuuu
-uuu uuuu
Rev. 1.30
12
March 6, 2009
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