HT46R49E Просмотр технического описания (PDF) - Holtek Semiconductor

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HT46R49E

Cost-Effective A/D Type 8-Bit MCU

Holtek Semiconductor 

HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E

M u s t a lw a y s b e s e t

fo r a n y r e a d o r w r ite

In fo r m a tio n d e p e n d s o n

ty p e o f r e a d o r w r ite

S ta rt 1 0 1 0 0 0 0 R /W A C K A d d re s s /D a ta

S to p

D e v ic e a d d r e s s R e a d = " 1 " A c k n o w le d g e

fix e d d a ta W r ite = " 0 " s ig n a l fr o m

EEPRO M

SDA

SDA

SDA

SCL

S ta r t C o n d itio n

SCL 8 9

A c k n o w le d g e

S D A p u lle d lo w b y

E E P R O M d u r in g

9 th c lo c k p u ls e

Data Transfer Protocol

SCL

S to p C o n d itio n

· START Condition

A start condition must be transmitted to the EEPROM

prior to transmitting the device address and before

any other address or data information is transmitted. A

start condition is implemented by a high to low transi-

tion on the SDA line with the SCL line high.

· Device Address

This must always immediately follow the transmitted

START condition and is implemented by clocking into

the EEPROM a ²1010000² 7-bit sequence. Clocking

the device address into the EEPROM is implemented

on the low to high edge of the SCL line. The data on

the SDA line must therefore be stable before the SCL

line changes from low to high. Any changes on the

SDA line when the SCL line is high could be inter-

preted as a START or STOP condition.

· R/W Bit

This follows the device address sequence and

informs the EEPROM if a read or write operation is to

be implemented. For a read operation, this bit should

be high, for a write operation the bit should be low.

· Acknowledge

After the EEPROM has successfully received any

8-bits of information, it will transmit an acknowledge

signal by pulling the SDA line low. A clock pulse for this

EEPROM generated acknowledge signal, which will

be the ninth clock pulse, must be supplied on the SCL

pin. Therefore after the 7-bit device address and the

R/W bit, which constitutes a total of 8-bits, has been

transmitted to the EEPROM, on the next clock cycle

the EEPROM will respond with an acknowledge sig-

nal. After this, the 8-bit data address information can

then be sent to the EEPROM, after which again the

EEPROM will respond with an acknowledge, on the

ninth clock pulse. Data information can then be trans-

mitted or received in a similar way.

· Data Address

Although the EEPROM internal data structure is

128´8 bits and as such requires a 7-bit address to ac-

cess the data, however an 8-bit address must be

transmitted to the EEPROM. The address is transmit-

ted in an MSB bit first format. As the 8th bit, which will

be the MSB and the first bit to be transmitted is redun-

dant, its value can be either zero or one. Note that the

address is clocked into the EEPROM on the low to

high edge of the SCL clock line.

· STOP Condition

A stop condition must be transmitted to the EEPROM

at the end of any read or write operation to terminate

the operation. The successful reception of a stop con-

dition by the EEPROM will cause it to enter its Power

Down Mode and await the next start bit. A stop condi-

tion is implemented by a low to high transition on the

SDA line with the SCL line high.

Rev. 1.20

18

August 15, 2007

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