HT46C48AE Просмотр технического описания (PDF) - Holtek Semiconductor

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HT46C48AE

Cost-Effective A/D Type 8-Bit MCU

Holtek Semiconductor 

HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E

EEPROM Data Memory

All devices contain an internal 1K capacity EEPROM

memory with a 128´8 bit structure. An EEPROM, which

stands for Electrically Erasable Programmable Read

Only Memory, is by its nature a non-volatile form of

memory, with data retention even when its power supply

is removed. By incorporating this kind of data memory, a

whole new host of application possibilities are made

available to the designer. The availability of EEPROM

storage allows information such as product identification

numbers, calibration values, specific user data, system

setup data or other product information to be stored di-

rectly within the product microcontroller.

Accessing the EEPROM Data Memory

The internal EEPROM Data Memory has an I2C struc-

ture and as such is accessed via a 2-line serial interface

for data transfer. These two lines are the Serial Data line

on pin SDA, and the Serial Clock line on pin SCL. The

SDA line is bi-directional and is the line where the data is

written to and read from the EEPROM. The SCL line is

an input line and is the clock signal for both the reading

and writing of data. These two EEPROM pins are

shared with I/O pins as shown in the table. Any pull-high

resistors configuration options for these pin shared pins

also remain valid for the EEPROM. Care must be taken

if these pins are used as normal I/O pins, as any signals

on the pins may be seen by the EEPROM as a valid read

or write operation command. If this happens the

EEPROM may inadvertently generate signals on its

SDA line which could create unexpected programming

errors. The Internal EEPROM can be directly controlled

using the pin-shared I/O pins or it can be directly con-

nected to an external I2C bus and controlled by some

other external master device. In this latter case care

should be taken to ensure that the pin-shared I/Os for

the SDA and SCL lines are both setup as inputs.

Function

EEPROM Pin

I/O Pin

Capacity

Device

HT46R46E/HT46R47E

SDA

SCL

PD0

PB3

128´8 bits

EEPROM I/O Shared Pins

HT46R48AE/HT46R49E

SDA

SCL

PC0

PC1

· SCL Pin

This is the clock input pin to the EEPROM. Writing

data into the EEPROM is implemented on the low to

high edge of this pin. Reading data out of the

EEPROM is implemented on the high to low edge.

Any data on the SDA line that is to be sent to the

EEPROM on the next rising clock edge is only allowed

to change state when the SCL line is low. If the SCL

line is high and the data on the SDA line changes, this

will be interpreted as a START or STOP condition.

· SDA Pin

This is the EEPROM data pin. As the pin is used for

both reading and writing of data it is bi-directional. As

the pin has an open-drain output, it can be wire-OR

connected to other external open-drain or

open-collector outputs. Otherwise it must be con-

nected to a pull-high resistor for correct operation,

which can be implemented using the pull-high config-

uration option for the corresponding shared I/O pin.

D a ta m u s t n o t c h a n g e w h e n S C L is h ig h

SDA

SCL

D a ta o n ly a llo w e d

to c h a n g e w h e n

S C L is lo w

Clock/Data Relationship

The sequence of events to read or write data to the

EEPROM follows the same pattern. All operations

must begin with a START condition and end with a

STOP condition. Inserted between the START and

STOP conditions are the device address, a read/write

bit and address and data information. All control infor-

mation, addresses and data is sent in 8-bit format to

the EEPROM, if successfully received the EEPROM

will respond with an acknowledge signal allowing the

next 8-bits to be received or transmitted.

Rev. 1.20

17

August 15, 2007

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