HT46R48 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT46R48

Cost-Effective A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R48

PW M

(6 + 2 ) C o m p a re

T o P D 0 C ir c u it

fS Y S

8 - s ta g e P r e s c a le r

fIN T

8 -1 M U X

TM 1

TM 0

P S C 2~P S C 0 TM R

TE

8 - B it T im e r /E v e n t

C o u n te r P r e lo a d

R e g is te r

D a ta B u s

R e lo a d

TM 1

TM 0

P u ls e W id th

M e a s u re m e n t

M o d e C o n tro l

TO N

8 - B it T im e r /E v e n t

C o u n te r

1 /2

O v e r flo w

to In te rru p t

PFD

Timer/Event Counter

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register will also

reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow

occurs. When the timer/event counter (reading TMR) is

read, the clock will be blocked to avoid errors. As clock

blocking may results in a counting error, this must be

taken into consideration by the programmer.

The bit0~bit2 of the TMRC can be used to define the

pre-scaling stages of the internal clock sources of

timer/event counter. The definitions are as shown. The

overflow signal of timer/event counter can be used to

generate the PFD signal.

Input/Output Ports

There are 19 bidirectional input/output lines in the

microcontroller, labeled as PA, PB, PC and PD, which

are mapped to the data memory of [12H], [14H], [16H]

and [18H] respectively. All of these I/O ports can be

used for input and output operations. For input opera-

tion, these ports are non-latching, that is, the inputs

must be ready at the T2 rising edge of instruction ²MOV

A,[m]² (m=12H, 14H, 16H or 18H). For output operation,

all the data is latched and remains unchanged until the

output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PCC, PDC) to control the input/output configuration.

With this control register, CMOS output or Schmitt trig-

ger input with or without pull-high resistor structures can

be reconfigured dynamically (i.e. on-the-fly) under soft-

ware control. To function as an input, the corresponding

latch of the control register must write ²1². The input

source also depends on the control register. If the con-

trol register bit is ²1², the input will read the pad state. If

the control register bit is ²0², the contents of the latches

will move to the internal bus. The latter is possible in the

²read-modify-write² instruction.

D a ta B u s

W r ite C o n tr o l R e g is te r

C h ip R e s e t

R e a d C o n tr o l R e g is te r

W r ite D a ta R e g is te r

C o n tr o l B it

DQ

CK Q

S

P u ll- H ig h

O p tio n

D a ta B it

DQ

CK Q

S

V DD

P A 0~P A 2

P A 3 /P F D

P A 4 /T M R

P A 5 /IN T

P A 6,P A 7

P B 0 /A N 0 ~ P B 3 /A N 3

P B 4~P B 7

P C 0~P C 1

P D 0 /P W M

(P D 0

orP W

M

)

PA3

PFD

R e a d D a ta R e g is te r

S y s te m W a k e -u p

( P A o n ly )

IN T fo r P A 5 O n ly

T M R fo r P A 4 O n ly

M

U

X

PFD EN

M

U

(P A 3 )

X

W a k e - u p o p tio n

Input/Output Ports

Rev. 1.10

15

March 24, 2006

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