HT46C22 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT46C22

8-Bit A/D Type MCU

Holtek Semiconductor 

HT46R22/HT46C22

well controlled, the original control sequence will be dam-

aged once the ²CALL² operates in the interrupt subrou-

tine.

Oscillator Configuration

There are two oscillator circuits in the microcontroller.

Both are designed for system clocks, namely the RC os-

cillator and the Crystal oscillator, which are determined

by the options. No matter what oscillator type is se-

lected, the signal provides the system clock. The HALT

mode stops the system oscillator and ignores an exter-

V DD

O SC1

O SC1

O SC2

fS Y S /4

O SC2

N M O S O p e n D r a in

C r y s ta l O s c illa to r

R C O s c illa to r

System oscillator

nal signal to conserve power.

If an RC oscillator is used, an external resistor between

OSC1 and VSS is required and the resistance must

range from 30kW to 750kW. The system clock, divided

by 4, is available on OSC2, which can be used to syn-

chronize external logic. The RC oscillator provides the

most cost effective solution. However, the frequency of

oscillation may vary with VDD, temperatures and the

chip itself due to process variations. It is, therefore, not

suitable for timing sensitive operations where an accu-

rate oscillator frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift required for the oscillator, and no other external

components are required. Instead of a crystal, a resona-

tor can also be connected between OSC1 and OSC2 to

get a frequency reference, but two external capacitors in

OSC1 and OSC2 are required (If the oscillating fre-

quency is less than 1MHz).

The WDT oscillator is a free running on-chip RC oscillator,

and no external components are required. Even if the sys-

tem enters the power down mode, the system clock is

stopped, but the WDT oscillator still works with a period of

approximately 65ms@5V. The WDT oscillator can be dis-

abled by options to conserve power.

Watchdog Timer - WDT

The clock source of the WDT is implemented by an dedi-

cated RC oscillator (WDT oscillator) or instruction clock

(system clock divided by 4) decided by options. This

timer is designed to prevent a software malfunction or

sequence jumping to an unknown location with unpre-

dictable results. The watchdog Timer can be disabled by

an option. If the watchdog Timer is disabled, all the exe-

cutions related to the WDT result in no operation.

Once an internal WDT oscillator (RC oscillator with pe-

riod 65ms/@5V normally) is selected, it is divided by

212~215 (by option to get the WDT time-out period). The

minimum period of WDT time-out period is about

300ms~600ms. This time-out period may vary with tem-

perature, VDD and process variations. By selection the

WDT options, longer time-out periods can be realized. If

the WDT time-out is selected 215, the maximum time-out

period is divided by 215~216about 2.1s~4.3s.

If the WDT oscillator is disabled, the WDT clock may still

come from the instruction clock and operate in the same

manner except that in the halt state the WDT may stop

counting and lose its protecting purpose. In this situation

the logic can only be restarted by external logic. If the

device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit TO. Whereas in the

HALT mode, the overflow will initialize a ²warm reset² only

the PC and SP are reset to 0. To clear the contents of

WDT, three methods are adopted; external reset (a low

level to RES), software instructions, or a HALT instruction.

The software instructions include CLR WDT and the other

set - CLR WDT1 and CLR WDT2. Of these two types of

instruction, only one can be active depending on the op-

tions - ²CLR WDT times selection option². If the ²CLR

WDT² is selected (i.e. CLRWDT times equal 1), any exe-

cution of the CLR WDT instruction will clear the WDT. In

case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e.

S y s te m C lo c k /4

W DT

O SC

O p tio n fS

S e le c t

D iv id e r

fS /2 8

W D T P r e s c a le r

M a s k O p tio n

CK T

R

W D T C le a r

Watchdog Timer

CK T

R

T im e - o u t R e s e t

fS /2 1 5 ~ fS /2 1 6

fS /2 1 4 ~ fS /2 1 5

fS /2 1 3 ~ fS /2 1 4

fS /2 1 2 ~ fS /2 1 3

Rev. 1.30

11

June 10, 2003

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