HT46R12A Просмотр технического описания (PDF) - Holtek Semiconductor

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HT46R12A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

operation. These areas may function as normal pro-

gram memory depending upon requirements.

Stack Register - STACK

This is a special part of the memory which is used to

save the contents of the program counter only. The

stack is organized into 8 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer, SP, and is neither readable nor writeable.

At a subroutine call or interrupt acknowledge signal, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

indicated by a return instruction, RET or RETI, the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledge signal will be inhibited. When the stack

pointer is decremented, using RET or RETI, the inter-

rupt will be serviced. This feature prevents a stack over-

flow allowing the programmer to use the structure more

easily. In a similar case, if the stack is full and a ²CALL²

is subsequently executed, a stack overflow will occur

and the first entry will be lost as only the most recent 8

return addresses are stored.

Data Memory - RAM

The data memory has a capacity of 115´8 bits, and is di-

vided into two functional groups, namely the special

function registers and the general purpose data mem-

ory (88´8 bits), most of which are readable/writeable,

although some are read only.

The unused space before address 28H is reserved for

future expansion usage and reading these locations will

obtain a result of ²00H². The general purpose data

memory, addressed from 28H to 7FH is used for data

and control information under instruction commands.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

the memory pointer registers, MP0 and MP1.

HT46R12A

00H

In d ir e c t A d d r e s s in g R e g is te r 0

01H

M P0

02H

In d ir e c t A d d r e s s in g R e g is te r 1

03H

M P1

04H

05H

ACC

06H

PCL

07H

TB LP

08H

TB LH

09H

0A H

STATU S

0B H

IN T C 0

0C H

0D H

TM R 0

0E H

TM R 0C

0FH

10H

TM R 1

11H

TM R 1C

12H

PA

13H

PAC

14H

PB

15H

PBC

16H

PC

17H

PCC

S p e c ia l P u r p o s e

D a ta M e m o ry

18H

19H

1A H

1B H

1C H

C M P 0C

1D H

C O M 1C

1E H

IN T C 1

1FH

20H

P P G 0C

21H

PPG T0

22H

23H

24H

ADRL

25H

ADRH

26H

ADCR

27H

ACSR

28H

G e n e ra l P u rp o s e

D a ta M e m o ry

:U nused

(8 8 B y te s )

7FH

R e a d a s "0 0 "

RAM Mapping

Rev. 1.00

8

August 3, 2007

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