HT46R12A Просмотр технического описания (PDF) - Holtek Semiconductor

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HT46R12A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R12A

The A/D converter interrupt is initialised by setting the

A/D converter request flag (ADF; bit 6 of the INTC1),

caused by an end of A/D conversion. When the interrupt

is enabled, the stack is not full and the ADF is set, a sub-

routine call to location 018H will occur. The related inter-

rupt request flag, ADF, will be reset and the EMI bit

cleared to disable further interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgements are held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1, if the stack is not full. To

return from the interrupt subroutine, a RET or RETI

instruction may be executed. The RETI instruction will set

the EMI bit to re-enable an interrupt service, but the RET

will not.

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source

Priority Vector

Comparator 0 output interrupt

1

004H

Comparator 1 output interrupt

2

008H

External Interrupt - from PC1

3 00CH

Timer/Event Counter 0 overflow

4

010H

Timer/Event Counter 1 overflow

5

014H

A/D converter completed overflow 6

018H

The EMI, EC0I, EC1I, EEI, ET0I, ET1I, and EADI bits

are all used to control the enable/disable status of the in-

terrupts. These bits prevent the requested interrupt from

being serviced. Once the interrupt request flags, C0F,

C1F, EIF, T0F, T1F, ADF are set, they remain in the

INTC1 or INTC0 register until the interrupts are serviced

or cleared by a software instruction. It is recommended

that a program does not use the ²CALL subroutine² within

the interrupt subroutine. Interrupts often occur in an un-

predictable manner or need to be serviced immediately in

some applications. If only one stack is left and enabling

the interrupt is not well controlled, the original control se-

quence will be damaged if the ²CALL² operates within the

interrupt subroutine.

Oscillator Configuration

V DD

O SC1

O SC1

O SC2

fS Y S /4

O SC2

N M O S O p e n D r a in

C r y s ta l O s c illa to r

R C O s c illa to r

System Oscillator

There are two types of system oscillator circuits within the

microcontroller. These are an RC oscillator and a Crys-

tal oscillator, the choice of which is determined via a

configuration option.

If an RC oscillator is used, an external resistor between

OSC1 and VSS is required and whose resistance

should range from 24kW to 1MW. Pin OSC2 can be

used to monitor the system frequency at 1/4 the system

frequency or can be used to synchronize external cir-

cuitry. The RC oscillator provides the most cost effec-

tive means of oscillator implementation, however, the

frequency of oscillation may vary with VDD, tempera-

ture and process variations. It is, therefore, not recom-

mended for use in timing sensitive applications where

an accurate oscillator frequency is desired.

If a Crystal oscillator is used, a crystal connected be-

tween OSC1 and OSC2 is required. No other external

components are required. Instead of a crystal, a resona-

tor can also be connected between OSC1 and OSC2 to

obtain a frequency reference, but two external capaci-

tors connected between OSC1, OSC2 and ground are

required, if the oscillating frequency is less than 1MHz.

When the system enters the Power-down mode the sys-

tem oscillator is stopped to conserve power.

The WDT oscillator is a free running on-chip RC oscillator,

and no external components are required. Even if the sys-

tem enters the power down mode where the system clock

is stopped, the WDT oscillator will continue to operate with

a period of approximately 65ms at 5V. The WDT oscillator

can be disabled using a configuration option to conserve

power.

Watchdog Timer - WDT

The WDT clock source is implemented using a dedi-

cated internal RC oscillator (WDT oscillator) or by the in-

struction clock, which is the system clock divided by 4.

The choice of which one is used is determined by a

configuration option. This timer is designed to prevent a

software malfunction or a sequence jumping to an un-

known location with unpredictable results. The

Watchdog Timer can be disabled by a configuration op-

tion. If the Watchdog Timer is disabled, all instructions

relating to the WDT result in no operation.

The WDT clock source will be subsequently divided by

either 213, 214 , 215 or 216, determined by a configuration

option, to get the actual WDT time-out period. Using the

internal WDT clock source, the minimum WDT time-out

period is about 600ms. This time-out period may vary

with temperature, VDD and process variations. By se-

lecting appropriate WDT options, longer time-out peri-

ods can be implemented. If the WDT time-out is

selected to be fS/216, then a maximum time-out period of

about 4.7s can be achieved.

Rev. 1.00

11

August 3, 2007

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