HT46R12 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT46R12

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R12

Bit No.

0~2

3

4

5

6

7

Label

¾

T1E

T1ON

¾

T1M0

T1M1

Function

Unused bit, read as ²0²

Defines the TMR1 active edge of the timer/event counter:

In Event Counter Mode (T1M1,T1M0)=(0,1):

1:count on falling edge;

0:count on rising edge

In Pulse Width measurement mode (T1M1,T1M0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

Enable/disable timer counting

(0= disable; 1= enable)

Unused bit, read as ²0²

Define the operating mode (T1M1, T1M0)

01= Event count mode (External clock)

10= Timer mode (Internal clock)

11= Pulse Width measurement mode (External clock)

00= Unused

TMR1C (11H) Register

Programmable Pulse Generator - PPG

This device provides one 8-bit PPG output channels.

Each PPG has a programmable period of 256´T, where

²T² can be 1/fSYS, 2/fSYS, 4/fSYS, 8/fSYS, 16/fSYS, 32/fSYS,

64/fSYS, 128/fSYS for an output pulse width.

The PPG detects the falling edge of a trigger input, and

outputs a single pulse, the falling edge trigger may come

from comparators or software trigger bit, which can be

selected by software. The PPG is capable of generating

signals from 0.25ms to 8.192ms pulse width when the

system frequency is operating at 4MHz. The PPG can

set the polarity control bit (P0LEV) as active low or ac-

tive high output (by mask option). A ²00H² data write to

the PPGT0 register yields a pulse width 256´T output.

· PPG0 functional description

The PPG0 module consists of PPG0 timers, a PPG

Mode Control, and two comparators. The PPG0 timer

consists of a prescaler, one 8-bit up-counter timer,

and an 8-bit preload data register. The programmable

pulse generator (PPG) starts counting at the current

contents in the preload register and ends at ²FFH®

00H². Once an overflow occurs, the counter is re-

loaded from the PPG0 timer counter preload register,

and generates a signal to stop the PPG timer. The

software trigger bit (P0ST) will be cleared when a

PPG timer overflow occurs.

There are two registers related to the PPG0 output

function, a control registers PPG0C and a timer

preload register PPGT0. The control registers PPG0C

define the PPG0 input control mode (trigger source),

enable or disable the comparators, define the PPG0

timer prescaler rate, range form fSYS/1, fSYS/2, fSYS/4,

fSYS/8, fSYS/16, fSYS/32, fSYS/64, fSYS/128, enable or dis-

able stopping the PPG0 timer using C0VO triggered

input, enable or disable the restarting of the PPG0

timer using C1VO triggered input, and control the

PPG0 software trigger bit to trigger the PPG0 timer On

or Off. The PPGT0 is the PPG0 preload register

preload register, the register contents decide the out-

put pulse width.

P C 1 /C 0 V IN +

+

P C 0 /C 0 V IN -

-

P C 2 /C 0 O U T

C 1 V IN +

+

C 1 V IN -

-

P C 3 /C 1 O U T

Rev. 1.00

D a ta b u s

C 0V O

P r e lo a d R e g is te r

R e lo a d

P P G M ode

C o n tro l

C 1V O

P P G 0 T im e r O n /O ff

P P G 0 T im e r

P P G 0 T im e r O ff

P 0 fs

P r e s c a le r

fS Y S

P 0 L E V ( O p tio n )

P 0P S C 2

P 0P S C 1

P 0P S C 0

PPG Block Diagram

P P G 0 O u tp u t

O v e r flo w

PPG

17

November 1, 2005

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