HT46R12 Просмотр технического описания (PDF) - Holtek Semiconductor

Номер в каталоге

Компоненты Описание

производитель

HT46R12

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the program counter and SP, leav-

ing the other circuits in their original state. Some regis-

ters remain unchanged during other reset conditions.

Most registers are reset to the ²initial condition² when

the reset conditions are met. By examining the PDF and

TO flags, the program can distinguish between different

²chip resets².

TO PDF

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² means unchanged

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

An extra option load time delay is added during a system

reset (power-up, WDT time-out at normal mode or RES

reset).

VDD

RES

tS S T

S S T T im e - o u t

C h ip R e s e t

Reset Timing Chart

HT46R12

The functional unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler, Divider

Cleared

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter Off

PPG Timer

Off

PPG output

Floating

Input/Output Ports Input mode

Stack Pointer

Points to the top of the stack

V DD

0 .0 1 m F *

100kW

RES

10kW

0 .1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

H A LT

W DT

W a rm R e s e t

RES

O SC1

SST

1 0 - b it R ip p le

C o u n te r

C o ld

R eset

S y s te m R e s e t

Reset Configuration

Rev. 1.00

13

November 1, 2005

Share Link: