HT46R065V Просмотр технического описания (PDF) - Holtek Semiconductor
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HT46R065V Datasheet PDF : 72 Pages
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HT46R065V
Ta=25°C
Symbol
Parameter
Test Conditions
VDD
Conditions
Min. Typ. Max. Unit
tPHL,
tPLH
Propagation Delay Time
(Clock to VFD Output)
Propagation Delay Time
(Strobe to VFD Output)
¾ VCC=15V
¾ 100 200 ns
¾ 100 200 ns
tTHL,
tTLH
tSU
Transition Time
Data Setup Time
¾ VCC=15V
¾ VCC=15V
¾
40
80
ns
¾
10
20
ns
tCS
Setup Time (Clock to Strobe)
VCC=15V
¾
10
20
ns
tH
Hold Time (Data to Clock)
VCC=15V
¾
10
20
ns
tSC
Hold Time (Clock to Strobe)
VCC=15V
¾
75 150 ns
tr, tf
Clock Input Rise or Fall Time
¾ VCC=15V
¾
¾
20
ns
tWC
Clock Pulse Width
¾ VCC=15V
¾
40
83
ns
tWL
Strobe Pulse Width
¾ VCC=15V
¾
35
70
ns
fmax
Maximum Clock Input Frequency ¾ VCC=15V
¾
8
¾ MHz
Note:
1. tSYS=1/fSYS
2. *For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Rev. 1.00
8
October 20, 2009
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