HT48R30A-1 Просмотр технического описания (PDF) - Holtek Semiconductor

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HT48R30A-1

I/O Type 8-Bit MCU

Holtek Semiconductor 

HT48R30A-1/HT48C30-1

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledge signal will be inhibited. When the stack

pointer is (by RET or RETI), the interrupt will be ser-

viced. This feature prevents stack overflow allowing the

programmer to use the structure more easily. In a similar

case, if the stack is full and a ²CALL² is subsequently

executed, stack overflow occurs and the first entry will

be lost (only the most recent 4 return addresses are

stored).

Data Memory - RAM

The data memory is designed with 115´8 bits. The data

memory is divided into two functional groups: special

function registers and general purpose data memory

(96´8). Most are read/write, but some are read only.

The special function registers include the indirect ad-

dressing registers (R0;00H), timer/event counter

(TMR;0DH), timer/event counter control register

(TMRC;0EH), program counter lower-order byte regis-

ter (PCL;06H), memory pointer registers (MP;01H), ac-

cumulator (ACC;05H), table pointer (TBLP;07H), table

higher-order byte register (TBLH;08H), status register

(STATUS;0AH), interrupt control register (INTC;0BH),

Watchdog Timer option setting register (WDTS;09H),

I/O registers (PA;12H, PB;14H, PC;16H, PG;1EH) and

I/O control registers (PAC;13H, PBC;15H, PCC;17H,

PGC;1FH). The remaining space before the 20H is re-

served for future expanded usage and reading these

locations will get ²00H². The general purpose data

memory, addressed from 20H to 7FH, is used for data

and control information under instruction commands.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP).

Indirect Addressing Register

Location 00H is indirect addressing register that is not

physically implemented. Any read/write operation of

[00H] will access data memory pointed to by MP. Read-

ing location 00H itself indirectly will return the result

00H. Writing indirectly results in no operation.

The memory pointer register (MP) is 7-bit registers.

Accumulator

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

00H

In d ir e c t A d d r e s s in g R e g is te r

01H

MP

02H

03H

04H

05H

ACC

06H

PCL

07H

TB LP

08H

TB LH

09H

W D TS

0A H

STATU S

0B H

IN T C

0C H

0D H

TM R

0E H

TM R C

0FH

10H

11H

12H

PA

13H

PAC

14H

PB

15H

PBC

16H

PC

17H

PCC

18H

19H

1A H

1B H

1C H

1D H

1E H

PG

1FH

PG C

20H

G e n e ra l P u rp o s e

D ATA M EM O R Y

(9 6 B y te s )

7FH

S p e c ia l P u r p o s e

D ATA M EM O R Y

:U nused

R e a d a s "0 0 "

RAM Mapping

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic opera-

tions. The ALU provides the following functions:

· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

· Logic operations (AND, OR, XOR, CPL)

· Rotation (RL, RR, RLC, RRC)

· Increment and Decrement (INC, DEC)

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation

but also changes the status register.

Rev. 2.00

8

April 24, 2009

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